Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help me out with a cross clock domain design

Status
Not open for further replies.
E

EDA_hg81

Advanced Member level 2
Advanced Member level 2
Joined
Nov 25, 2005
Messages
507
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,808
In my design, a local clock is generated by a clock divider, which looks like follow:

process ( iARM7_CLK )
begin
if ( rising_edge( iARM7_CLK ) ) then
spiclkcon <= spiclkcon + 1;
if ( spiclkcon = spiclk_gen ) then
spiclkcon <= x"00";
spiclk <= not spiclk;
elsif ( spiclkcon = x"32" and spiclk = '0' ) then
.. check the data from ARM7 CLOCK domain…
Click to expand...
But I have to capture data generated in ARM7_CLOCK domain and have to send data back to ARM7 clock domain.

My question is:

What is the proper way to do those ideas? What I should do to keep those data are valid when they transfer clock domain.

I can not use buffer which is driven by two clocks.

Thanks.
 

Re: Cross clock domain

whato you should do is keep using your , let's call it system clock, and the use your devided clock as clock enable.

if risinge_edge(sys_clk) then

if divide_clk = '1' then
(
put your logic here;

)

your outputs are now aligned with system clock.
pay attentio your outputs to your domain are now allign with sys_clk, and not divide_clk. so you need to shift them.
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Cross clock domain

it is not really CDC since you using only one clock to produce divided clock, both of those clocks will be in same phace.

CDC means when you are crossing domain between two clocks and there is no any relationship between those clocks
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Re: Cross clock domain

Code: 
if ( rising_edge( iARM7_CLK  ) ) then
                 spiclkcon <= spiclkcon + 1;
                 if ( spiclkcon = spiclk_gen ) then
                     spiclkcon <= x"00";
                     spiclk    <= not spiclk;
                 elsif (  spiclkcon = x"05" and  spiclk = '0' ) then
                     case readstatus is
                          when x"00" =>
                              if (  iSD_BUF(7) = '1' ) then 
                                   command <= command09;
                               readstatus  <= readstatus + 1;
                              elsif (  iSD_BUF(6) = '1' )then
                                   command <= command09;
                               readstatus  <= readstatus + 1;
                              end if;

Do you think code like above is right?
 

Cross clock domain

looks about right, but I was told you before, you should separate your processes, make code more readble, and also make compilier job easy. Also when you read your timing report, it makes more easy to analyze when you have more structured code

good lack
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Re: Cross clock domain

Thank you all for help.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top