Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[10 point for real help] Voltage pb

Status
Not open for further replies.

mouzid

Full Member level 5
Full Member level 5
Joined
Jun 22, 2007
Messages
248
Helped
9
Reputation
18
Reaction score
0
Trophy points
1,296
Activity points
2,876
Hi all,
Using a cadence platform I designed a module that generate a square wave of 1 Volt amplitude. When I connect this one to another module the voltage scale to 0.7 V.
I used 2 inverter between the 2 modules but the problem persists.
How can I resolve this problem ?
 

some schematic will help
 

    mouzid

    Points: 2
    Helpful Answer Positive Rating
Nop, i meant schematic of what is inside the module :D
 

    mouzid

    Points: 2
    Helpful Answer Positive Rating
I suppose its a PLL that is generating the square wave. you need to insert a buffer with an appropriate number of stages & proper sizing. You can read Digital Integrated circuits by Rabaey for details on Buffers(chap 5). Various factors like the load Cap & Cap of the generator([PLL) affect this. You can also try increasing the W/L's of the inverters that u have inserted as it is possible that the inverter is not able to drive the load. Sometimes when shifting between analog to digital or vice versa u require level shifters too.you can try using a level shifter followed by a buffer too. Hope this helps.

Added after 4 minutes:

This should help, slides from rabaey.
 

    mouzid

    Points: 2
    Helpful Answer Positive Rating
I suspect something wrong with the module-2, Can you give the input stage schema of module-2
 

The second module could be loading your first stage.

Instead of the second try it out with a capacitve load, which should give u an estimate of the capacitance to keel the voltage at 0.7 volts then resixe the output with some buffers.

Or add level restores with a psuedo pmos at thee input of the second stage.
 

    mouzid

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top