EDA_hg81
Advanced Member level 2
Clock
I have used a input clock( 50MHZ) to generate another clock( 250KHZ) by using simple counter.
Which kind of buffer I should use for increasing the fan out ability of this 250KHZ clock?
The FPGA I am using is Spartan 3.
Thanks.
I have used a input clock( 50MHZ) to generate another clock( 250KHZ) by using simple counter.
Which kind of buffer I should use for increasing the fan out ability of this 250KHZ clock?
The FPGA I am using is Spartan 3.
Thanks.