Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

My VHDL tricks collection.

Status
Not open for further replies.
K

kelvin_sg

Advanced Member level 4
Full Member level 1
Joined
Aug 17, 2004
Messages
102
Helped
3
Reputation
6
Reaction score
3
Trophy points
1,298
Location
Singapore
Activity points
852
vhdl tricks

Another VHDL arithmetic question!
Regarding signed multiplication C = A*B;
Syntax-wize NC = NA + NB, with 1 extra bit just to take care of CMAX = (-2^(NA-1))*(-2^(NB-1))?


In Verilog we use NC = NA + NB - 1 with (-AMAX)*(-BMAX) tied to CMAX-1.
Click to expand...
 

vhdl tricks methodologies

Code: 
my_sum <= '1' & (WIDTH_c-2 downto 1 => '0') & '1' ;
 
verilog tricks

My first trick..

Code: 
signal	my_sum	: std_logic_vector(WIDTH_c-1 downto 0);  

...
my_sum(WIDTH_c-1) <= '1';
my_sum(0) <= '1';
my_sum(WIDTH_c-2 downto 1) <= (others=>'0');

How do I replace the above assignment with one-liner?

Thanks!
Click to expand...
shnain said:
Code: 
my_sum <= '1' & (WIDTH_c-2 downto 1 => '0') & '1' ;
Click to expand...

Yeah. Thank you!

Another one..
In IF statement, how do I use "others"?
My BIT_SEL1 and BIT_SEL2 are constants..

if (my_sum(BIT_SEL1-1 downto BIT_SEL2-1) /= (others=>'0')) then
blah blah;
end if
 

vhdl trick

if <condition> then
.....
else ----(others)
.....
end if.

Added after 4 seconds:

if <condition> then
.....
else ----(others)
.....
end if.
 

bit trick vhdl

vikas_lakhanpal27 said:
if <condition> then
.....
else ----(others)
.....
end if.

Added after 4 seconds:

if <condition> then
.....
else ----(others)
.....
end if.
Click to expand...

It's a method.. but too complicated..
I like best is one liner..:D

I declare an extra variable to handle that.
 

tricks for vhdl

Please post if you have any more tricks!!
 

NanhTrang said:
Please post if you have any more tricks!!
Click to expand...

I just shifted from Verilog to VHDL, so this thread is intended to ACCUMULATE
my favorite tricks. :D

Next Question:

Regarding parameterization..

How shall I deal with my_sig(NA downto NB) when NA == NB?
When coding with parameters, this situation can happen. In Verilog my_sig(NA downto NA) is valid.. :idea:

Added after 5 hours 30 minutes:

Regarding signed multiplication C = A*B;
Is NC = NA + NB?

Logically it should be NC = NA + NB - 1?

Magnitude = 2^(NA-1 + NB-1);
+ 1 Sign bit
= NA_NB-1?
 

How shall I deal with my_sig(NA downto NB) when NA == NB?
When coding with parameters, this situation can happen. In Verilog my_sig(NA downto NA) is valid.. Idea
Click to expand...

This is also valid in VHDL :)

Enjoy!
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top