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Doubt regarding deriving clock for ADC from FPGA kit.

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sita

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fpga adc

Dear frnds,

myself doing project on Real-time Spectrum Analyzer using FPGA. During the process, we are planning to use Speech signal inputted through microphone.
I need an ADC and FPGA (used for implementing frequency transformation.)
We are planning to provide sampling clock to ADC from FPGA kit. Presently, we have Spartan-III kit.

How can I provide sampling clock of 44 kHz from 4MHz crystal in FPGA. There are only FRC cables for I/O pins in the kit. Should I need to write program for frequency division & take that output & provide to ADC. Is it possible? Pls do help with your suggestions for the same.
 

fpga adc clock

Hello,

I don't know what ADC you intend to use. I think, for audio application a serial interfaced ADC would be appropriate, e. g. an industy standard audio codec. Many eval kits supply some of these on-board. Typically, I would generate all clocks from FPGA, cable connection shouldn't be an issue in your frequency range, you should minimize the length if possible. For fast signals, parallel or series termination could be meaningful.

I guess, you should expect more serious challenges in the project than clocking an ADC.

Regards,
Frank
 

    S

    sita

    Points: 2
    Helpful Answer Positive Rating
fpga clock adc

The common digital audio sample rate (such as a music CD player) is 44.1 kHz, not 44 kHz. However, unless you require compatibility with other digital audio equipment, the exact sample rate may not be important in your application.

If you really need 44.1 kHz, and if your FPGA clock is only 4 MHz (that's a really slow clock), then you could feed the 4 MHz clock into a DCM that's configured for 21/20 frequency synthesis, then feed its output into another DCM that's also configured for 21/20 synthesis, and then feed its output into a divide-by-100 counter. The result will be 44.1 kHz, within the accuracy of your crystal oscillator.
4000000 * 21/20 * 21/20 / 100 = 44100

I've never tried feeding such a low clock frequency into a Spartan-3 DCM frequency synthesizer, but the data sheet says it should work.
 

    S

    sita

    Points: 2
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adc with fpga

Hello,

as far as I know (I'm more familiar to Altera FPGA), Spartan-3 DCM can't use clock output frequency below 18 MHz in the discussed configuration. I don't know if chaining of two DCM with an clock divider in between is possible here.

However, I guess that keeping a nominal sampling rate isn't mandatory for the said application. Even for an audio application 0.23 % frequency deviation would be almost unhearable without a reference. You always should be able to get this accuracy with single DCM frequency multiplication and following integer division. Even the 43.96 kHz achievable with 4 MHz integer division would be possibly accurate enough, although I guess, that the system would use a higher base clock frequency for signal processing, maybe 20..50 MHz for optimal performance and easy timing closure.

Regards,
Frank
 

adc kit audio

Oops, yes, I just remembered that too! :oops: I'll try to find a way to fix it . . .

<some time passes>

Oh great. I have a solution ready to try, but I can't test it because XST is giving me "FATAL_ERROR" crash messages . . .

<more time passes>

Ok, I solved the FATAL_ERROR messages by replacing my BUFGMUX primitives with BUFG primitives. Go figure!

Here's a new paragraph to replace my earlier paragraph. I tested it by compiling the following Verilog code into my Spartan-3 board, and feeding it a 4 MHz clock. The output reads 44100.0 Hz on my frequency counter.

If you really need 44.1 kHz, and if your FPGA clock is only 4 MHz (that's a really slow clock), then you could feed the 4 MHz clock into a DCM that's configured for 21/2 frequency synthesis, then feed its output into another DCM that's configured for 21/20 synthesis, and then feed its output into a divide-by-1000 counter. The result will be 44.1 kHz, within the accuracy of your crystal oscillator.
4000000 * 21/2 * 21/20 / 1000 = 44100

Code: 
module sample (clk4mhz, out44100);
  input         clk4mhz;
  wire          clka, clkb, clkc, clkd, locked;
  reg     [4:0] reset=0;
  reg     [9:0] count=0;
  output        out44100;

  // synthesize 4 MHz * 21/2 * 21/20 / 1000 = 44100 Hz
  DCM dcm1 (.CLKIN(clk4mhz), .RST(1'b0), .CLKFB(), .CLK0(), .CLKDV(), .CLKFX(clka), .LOCKED(locked));
  defparam dcm1.CLK_FEEDBACK       = "NONE";
  defparam dcm1.CLKFX_MULTIPLY     = 21;
  defparam dcm1.CLKFX_DIVIDE       = 2;
  defparam dcm1.CLKIN_PERIOD       = 250;
  defparam dcm1.DFS_FREQUENCY_MODE = "LOW";

  BUFG buf1 (.I(clka), .O(clkb));

  always @ (posedge clkb)
    reset <= {reset,locked};

  DCM dcm2 (.CLKIN(clkb), .RST(~reset[4]), .CLKFB(), .CLK0(), .CLKDV(), .CLKFX(clkc), .LOCKED());
  defparam dcm2.CLK_FEEDBACK       = "NONE";
  defparam dcm2.CLKFX_MULTIPLY     = 21;
  defparam dcm2.CLKFX_DIVIDE       = 20;
  defparam dcm2.CLKIN_PERIOD       = 23.8;
  defparam dcm2.DFS_FREQUENCY_MODE = "LOW";

  BUFG buf2 (.I(clkc), .O(clkd));

  always @ (posedge clkd)
    count <= count==1011 ? 12 : count + 1;  // divide-by-1000 with square wave in bit 9

  assign out44100 = count[9];
endmodule
 

    S

    sita

    Points: 2
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digital clock on fpga kit

Thank you very much FvM and echo47 for your valuable suggestions.
Thank you echo 47 for your code, I will definitely try out, and let you know the result.
 

cascading digital clock manager

echo47 said:
Oops, yes, I just remembered that too! :oops: I'll try to find a way to fix it . . .

<some time passes>

Oh great. I have a solution ready to try, but I can't test it because XST is giving me "FATAL_ERROR" crash messages . . .

<more time passes>

Ok, I solved the FATAL_ERROR messages by replacing my BUFGMUX primitives with BUFG primitives. Go figure!

Here's a new paragraph to replace my earlier paragraph. I tested it by compiling the following Verilog code into my Spartan-3 board, and feeding it a 4 MHz clock. The output reads 44100.0 Hz on my frequency counter.

If you really need 44.1 kHz, and if your FPGA clock is only 4 MHz (that's a really slow clock), then you could feed the 4 MHz clock into a DCM that's configured for 21/2 frequency synthesis, then feed its output into another DCM that's configured for 21/20 synthesis, and then feed its output into a divide-by-1000 counter. The result will be 44.1 kHz, within the accuracy of your crystal oscillator.
4000000 * 21/2 * 21/20 / 1000 = 44100



always @ (posedge clkb)
reset <= {reset,locked};

always @ (posedge clkd)
count <= count==1011 ? 12 : count + 1; // divide-by-1000 with square wave in bit 9

assign out44100 = count[9];
endmodule[/code]
Click to expand...

hi there. I'm in the stage of learning verilog and fpga as well. Can anyone elaborate more on the code, not quite understand the purpose of the highlighted part. Some comments on that would be nice.

Wat i understand is u r cascading 2 DCM's. dcm1 is feeding with the master clock(4Mhz), dcm2 is feeding with the output of dcm1 through a BUFG. The output of dcm2 is feeding to something which i dun really understand the logic through a BUFG also. And the reset as well, quite blur.
 

4mhz verilog

Hi wakaka,

I used two cascaded DCM synthesizers because a single DCM doesn't have enough flexibility in its numerator and denominator to provide the required ratio.

The 4 MHz input clock 'clk4mhz' feeds into dcm1 which is configured as a 21/2 frequency synthesizer, so it's 'clka' output is 42 MHz.

When cascading two Xilinx DCMs, it's necessary to hold the second DCM in reset until the first DCM has stabilized and locked, plus a few additional clock cycles (that's mentioned somewhere in the Xilinx DCM documentation). That's the job of the 'reset' shift register. A shift register needs a good low-skew clock, so I buffered the weak 'clka' signal into global clock 'clkb'.

DCM 'dcm2' is configured as a 21/20 frequency synthesizer. Its 'clkb' input is 41 MHz, so its 'clkc' output is 44.1 MHz.

Signal 'clkc' is also weak, so I buffered it as global clock 'clkd' so it can reliably clock the divide-by-1000 counter. That counter divides the 44.1 MHz 'clkd' into the 44.1 kHz squarewave 'count[9]'. The 10-bit counter endlessly counts from 12 to 1011. I chose that peculiar range so bit 9 would be a perfect square-wave, just in case someone needed 50% duty cycle. If I had counted from 0 to 999, then bit 9 would have been non-square.

Xilinx ISE provides a software tool for generating DCM HDL code, and most people probably use it, but I prefer hand-writing my own code for small things like this.
 

adc fpga clock problems

echo47 said:
Hi wakaka,

I used two cascaded DCM synthesizers because a single DCM doesn't have enough flexibility in its numerator and denominator to provide the required ratio.

The 4 MHz input clock 'clk4mhz' feeds into dcm1 which is configured as a 21/2 frequency synthesizer, so it's 'clka' output is 42 MHz.

When cascading two Xilinx DCMs, it's necessary to hold the second DCM in reset until the first DCM has stabilized and locked, plus a few additional clock cycles (that's mentioned somewhere in the Xilinx DCM documentation). That's the job of the 'reset' shift register. A shift register needs a good low-skew clock, so I buffered the weak 'clka' signal into global clock 'clkb'.

DCM 'dcm2' is configured as a 21/20 frequency synthesizer. Its 'clkb' input is 41 MHz, so its 'clkc' output is 44.1 MHz.

Signal 'clkc' is also weak, so I buffered it as global clock 'clkd' so it can reliably clock the divide-by-1000 counter. That counter divides the 44.1 MHz 'clkd' into the 44.1 kHz squarewave 'count[9]'. The 10-bit counter endlessly counts from 12 to 1011. I chose that peculiar range so bit 9 would be a perfect square-wave, just in case someone needed 50% duty cycle. If I had counted from 0 to 999, then bit 9 would have been non-square.

Xilinx ISE provides a software tool for generating DCM HDL code, and most people probably use it, but I prefer hand-writing my own code for small things like this.
Click to expand...

Hi echo, thanks for the explaination. Understand that except one part, which is the divide by 1000 counter.

The 10-bit counter endlessly counts from 12 to 1011. I chose that peculiar range so bit 9 would be a perfect square-wave, just in case someone needed 50% duty cycle. If I had counted from 0 to 999, then bit 9 would have been non-square.

can't visualize it. When counting from 0-999, in binary 999 = 1111100111
When counting from 12-1011, 1011 = 1111110011.
Both counter[9] is 1, so...........how??can't get the square and non square thing.

another question, to get 44.1khz from 44.1mhz, can the 44.1mhz clkd being fed to another dcm which can divide the clock by 1000? or a dcm has limitations on the division factor?
 

adc with clock frequency of 4 mhz

When counting from 0 to 999, the binary values go from 0000000000 to 1111100111. Bit 9 is 0 for 512 clocks, and then 1 for 488 clocks. That's not quite 50% duty cycle.

When counting from 12 to 1011, the binary values go from 0000001100 to 1111110011. Bit 9 is 0 for 500 clocks, and then 1 for 500 clocks. That's 50% duty cycle, a square wave.

A Spartan-3 DCM frequency synthesizer can't divide by 1000. The DCM has several restrictions. The frequency ratio is M/N, where M is an integer between 2 and 32, and N is an integer between 1 and 32. Also, the DCM input must be between 1 MHz and 280 MHz, and the DCM output must be between 18 MHz and 210 MHz (some versions can go higher). Other Xilinx FPGA families have different restrictions. Most of these values are listed in the "switching characteristics" section of the data sheet.

A Xilinx FPGA contains only a few DCM's, so use them sparingly. A DCM also adds some period jitter.
 

output clock from fpga

echo,

Thanks. clear explanation. Just curious, how u know that counting from 0-999 got 512 clocks of 0 for bit 9, whereas counting from 12-1011 consists of equal numbers of 0 and 1 for bit9.
Any method to calculate that?
 

xilinx dcm chaining

I'm not sure how to explain the method I used to figure it out, but a smaller example should help illustrate what's happening.

Let's say we want to divide by ten and output a square wave.
If we build a 4-bit counter that counts endlessly from 0 to 9, the binary values are:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Bit 3 goes 0 0 0 0 0 0 0 0 1 1, which is divide-by-ten, but it isn't a square wave.

If we instead count from 3 to 12:
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bit 3 goes 0 0 0 0 0 1 1 1 1 1, which is a square wave.

There are of course other ways to divide by ten and output a square wave.
 

500 hz clock verilog code

dear echo,

I have some doubts in the code you gave. Please help me to clear that......

1) DCM dcm1 (.CLKIN(clk4mhz), .RST(1'b0), .CLKFB(), .CLK0(), .CLKDV(), .CLKFX(clka), .LOCKED(locked));

Is it necessary to specify, CLKFB, CLK0, CLKDV in port mapping. Since we are not using it, cant we better not mention that?

2) BUFG buf1 (.I(clka), .O(clkb));

I could simulate the above code without giving BUFG, then also it simulated. Will there be any problem if BUFG not used in synthesis?

Can't we use buf primitive instead of BUFG. Is there any advantage of specifically using BUFG over buf?

Regards,
sita
 

adc + fpga kit

1. Yes you can delete those unused ports. I keep them simply as reminders to myself. They are harmless.

2. If you don't insert a BUFG global clock buffer (or some other type of clock buffer provided by your particular type of FPGA), and if the synthesizer doesn't automatically insert one for you, then the 'clkb' clock signal will probably be routed through ordinary routing paths. The resulting large time skew can cause the 5-bit 'reset' shift register to malfunction, unless you use an SRL16 for the shift register (it uses only one clock net connection). Behavioral simulation doesn't consider clock skew, so it won't show any problem.

In modern Xilinx FPGAs, BUF is a phantom device that usually doesn't insert anything into your logic. (The ISE Libraries Guide even says "BUF is usually not necessary and is removed by the partitioning software".) I'm not sure what BUF is good for, except to conceptually split a signal so different constraints can be applied to the two segments.
 

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