Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The VHDL source generated from Simulink is only in structural format, i.e., it's not in the behaviral one that allows easy reading. Before you can even do that, you must convert your design to a set of available fixed/floating point library functions then re-simulate your design to make sure that it still meets the overall requirement. After that you can convert the design to either VHDL/Verilog.
Cheers,
-s
U should checkout the latest Matlab release which includes the Simulink HDL Coder that has the examples/tutorial material. Depending on what you have now or if u start a new project and so on. If you start a new one, you can look through the available library set of functions and work from there.
-s
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
