Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help me with my T&H circuit (SFDR and clock issues)

Status
Not open for further replies.
W

wael_wael

Full Member level 4
Full Member level 4
Joined
Dec 3, 2005
Messages
221
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,298
Activity points
2,760
Help in T&H circuit

i have designed OTA with following specifications:
Dc gain=72db, phase =62, fu=230Mhz
so i used switch capacitor architecture with the obove OTA, switches are designed by transmission gate techniuqe,
the problem is the SFDR, around 45db. also the clock designed for 100p rise time and fall time, how to increase the SFDR.
fs=5oMSps, resoluation=10 bit
pest regards
 

Help in T&H circuit

The timing of s/h is no-overlap? There is a large harmonic in your circuit. check the harmonic frequency. The do .tran simulation, check the SC-op settling.
 

    W

    wael_wael

    Points: 2
    Helpful Answer Positive Rating
Re: Help in T&H circuit

no the clock over lapping output, but the settling time was not good enouph, i will increase the current of hole circuit to get required settling time
thanx
 

Help in T&H circuit

The sample and hold colck should high level no overlapping. and check the sample timing, CM switch should turn off first then sample switch turn off and then hold switch on. that can reduce the charge injection and clock feedthrough.
 

Re: Help in T&H circuit

well, the clock rise time and fall time around 60 ps, the diferent between the clocks around 47p, i didnt use commone switch
regards
 

Re: Help in T&H circuit

CM switch should turn off first then sample switch turn off and then hold switch on. that can reduce the charge injection and clock feedthrough


How much time betteen that?

or How to deside it?
 

    W

    wael_wael

    Points: 2
    Helpful Answer Positive Rating
Re: Help in T&H circuit

i have small problem that is the clock has dalay 1 ns, the clock total time is 20 ns. can the clock dalay effect the SFDR
regards
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top