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Metal Density in Layoput

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metal density

Hi Friends,

Why we have to satisfy metal density in layout.
 

metal density layout

safwatonline said:
stress issues
Click to expand...

Stress means,which type of sress (Mechanical or Electrical).
 

density check in wafer fabrication

mechanical
 

layout metal density stress

for planarization purpose
 

rule metal density

Mostly for etching uniformity during fabrication.
 

metal density based problems

what does metal density means, is it thickness??
 

all metal by density

Metal density means how much metal in a given area. Typically foundries maintain at least certain percentage for unifomity. If it is not fulfilled, "dish bowling" effect may be seen.

For more advance technology, they may set a upper limit of density also
 

metal density on layout

I think stress is a problem, so we need to add some slot in large metal region
 

metal density of .38

Stress is a problem on large areas of metal but that is a different DRC check from the density check.
 

metal density rule

Metal density refers to the ratio of metal features to open features for a given metal mask. This is primarily a requirement for the Wafer Fab metal etch process, but can have implications for plasma damage too.
The process uses RIE (anisotropic plasma etch) which is very sensitive to the amount of resist (density) on the wafer during the etch. This is a limitation of the plasma chemistry required for aluminium etching. The erosion of the resist contributes to anisotropy of the etch.
If there is too little, despite being anisotropic, the etch will undercut narrow resist features which will become sub-design rule in width and compromise the IC. There is also a thin Ti-Nitride cap on top of the Aluminium-Copper which acts as an anti reflectant coating for the phtot imaging process. This is not undercut so the cross section of an aluminium track looks like a skinny mexican wearing a huge sombrero (appologies to any mexicans). This conductive TiN cap can now easily fall off and land somewhere else causing conductive shorts and yield loss.
Another problem is the track at the edge of a dense/isolated area. The side of the last track, the one facing the large isolated expanse, will tend to be sloped (undercut on one side) and therefore compromised. This is almost impossible to stop no matter what the density. So this goes into the Designers School Bag for Best Layout Practices - last line should not be minimum design rule width. Write that out 100 times!

If too dense, the non uniformity of the etch will become worse, so when the etch endpoints (the exposed open metal areas between tracks become clear of metal) because of non unform etch, there will be areas that have no yet cleared. Depending on layout, these islands of metal not yet cleared can become huge antennas for charge collection which then damages the IC local to these islands.

[Note that this can still be a problem in layout even when the density is very low, but is actually very dense in one particular area. The DRC will not find this and the route cause of failure (careless layout) never identified as the fab cannot see this during processing. So this also goes into the Designers School Bag of Best Layout Practices!! The Fab is not always to blame for Plasma Induced Damage - write that one out 1000 times.]

It is quite unusual for the metal density to be too dense, so may Foundries just specify a minimum (around 28%).

The stress issue is when the tracks are very long and very wide. The foundry should specify in the design rules, that large long narrow cut outs are included in any such layouts. This is mostly for power buses and can be a real problem at the corners of the device. The Foundries should catch this and some of them take the responsibility of placing them into a customer layout even if the customer does not.
 
Re: metal density rule

Colbhaidh said:
Metal density refers to the ratio of metal features to open features for a given metal mask. This is primarily a requirement for the Wafer Fab metal etch process, but can have implications for plasma damage too.
The process uses RIE (anisotropic plasma etch) which is very sensitive to the amount of resist (density) on the wafer during the etch. This is a limitation of the plasma chemistry required for aluminium etching. The erosion of the resist contributes to anisotropy of the etch.
If there is too little, despite being anisotropic, the etch will undercut narrow resist features which will become sub-design rule in width and compromise the IC. There is also a thin Ti-Nitride cap on top of the Aluminium-Copper which acts as an anti reflectant coating for the phtot imaging process. This is not undercut so the cross section of an aluminium track looks like a skinny mexican wearing a huge sombrero (appologies to any mexicans). This conductive TiN cap can now easily fall off and land somewhere else causing conductive shorts and yield loss.
Another problem is the track at the edge of a dense/isolated area. The side of the last track, the one facing the large isolated expanse, will tend to be sloped (undercut on one side) and therefore compromised. This is almost impossible to stop no matter what the density. So this goes into the Designers School Bag for Best Layout Practices - last line should not be minimum design rule width. Write that out 100 times!

If too dense, the non uniformity of the etch will become worse, so when the etch endpoints (the exposed open metal areas between tracks become clear of metal) because of non unform etch, there will be areas that have no yet cleared. Depending on layout, these islands of metal not yet cleared can become huge antennas for charge collection which then damages the IC local to these islands.

[Note that this can still be a problem in layout even when the density is very low, but is actually very dense in one particular area. The DRC will not find this and the route cause of failure (careless layout) never identified as the fab cannot see this during processing. So this also goes into the Designers School Bag of Best Layout Practices!! The Fab is not always to blame for Plasma Induced Damage - write that one out 1000 times.]

It is quite unusual for the metal density to be too dense, so may Foundries just specify a minimum (around 28%).

The stress issue is when the tracks are very long and very wide. The foundry should specify in the design rules, that large long narrow cut outs are included in any such layouts. This is mostly for power buses and can be a real problem at the corners of the device. The Foundries should catch this and some of them take the responsibility of placing them into a customer layout even if the customer does not.
Click to expand...

"Hi Colbhaidh, Can you please tell me when does the dishing problem arises? According to my understanding, when we are violating the maximum density rule check, meaning we are dumping more metal than what can be handled by the CMP(Chemical Mechanical Polishing). So that the weight of metal becomes to heavy to be handled by the oxide below and it dishes. Am I right ? "
 

Metal etching speed depends on how much surface covered.
To stay within acceptable etch tolerance is better to have certain metal density.
 

There are 2 things that improve if you have a good metal density on chip:
1. The etching of metal is uniform(we don't get shorts or opens, this rarely happens, and we can make sure that the metal has the same thickness all over)
2. After we deposit a layer o metal, the planarity of the chip will be very good for the next metal layer deposition process(planarity will help litography because all resist will be in focus)
 
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