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How to make a state machine of a sequence detector?

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spauls

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Can any body tells about how to proceed to make a state machine of a sequence detector ,
regards
 

so easy problem....

search 'sequence detector' in google.
 

somebody implemented it by fsm.
 

Re: Sequence Detector

use shift register and some logic is sufficient.

for exampl, if you want to detect sequence 1011,

you can use following verilog code to do it.

wire signal_in;
wire seq_detected;
reg signal_d1, signal_d2, signal_d3;

always @(posedge clk or negedge rst_n)
if (~rst_n)
begin
signal_d1 <= #1 1'b0;
signal_d2 <= #1 1'b0;
signal_d3 <= #1 1'b0;
end
else
begin
signal_d1 <= #1 signal_in;
signal_d2 <= #1 signal_d1 ;
signal_d3 <= #1 signal_d2 ;
end

assign seq_detected = signal_d3 & (~signal_d2) & signal_d1 & signal_in;

best regards







spauls said:
Can any body tells about how to proceed to make a state machine of a sequence detector ,
regards
Click to expand...
 

Re: Sequence Detector

The answer is described nicely here

**broken link removed**
 
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