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32 bit division in verilog

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sameem_shabbir

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verilog division

Hi all AOA

I need to divide two 32bit nos in verilog for my project which is on spartan3 starter
kit.
Another problem is that the answer of division is always b/w 0 and 1. i.e it is always in fractions(except for 1)

How should i do that. I need a code for that.[/i]
 

division in verilog

Try using "Divider Generator" or "Pipelined Divider" which are included with CORE Generator, which is included with ISE.
I'm not sure if they generate readable HDL, but they will give you a module that you can drop into your FPGA project.
 
division verilog

I was unable to find the core generator or the pipline divider
plz will u explain from where should i get it

Added after 1 hours 9 minutes:

sory i have found the core generator and the piplined divider
but the verilog file which core generator has generated contains a module instantiation (sdivider_v3_0)
from where should i get that code
 
verilog divider

Please clarify - do you need full Verilog code of the divider, or do you only need a working divider that you can drop into your Verilog project?

The Xilinx Pipelined Divider core may only give you an NGC file (containing compiled sdivider_v3_0) with no Verilog code. If that's true, then you can put the NGC file into your ISE project, instantiate the Verilog wrapper file, and now you have a working divider.
 
divider verilog code

I need a working divider

But the problem is
I dont get any NGC file
The core generator creates four files .veo, .asy, .sym, .v.
Now which file should i put in my project
Or do u want to say that i just instantiate the module and it will work
 

verilog div

No NGC file? That's weird. After you clicked "Generate", did you see any error messages?
Or maybe you accidentally selected an option that somehow causes the output files to be skipped.

After I generate the core, it creates these output files and displays a readme that briefly describes them:
div.v, div.veo, div.ngc, div.xco, div_xmdf.tcl, div_flist.txt, and div_readme.txt.

I'm using ISE 9.2.04i and ISE IP Update 2. Be sure you've updated your version of ISE with the latest "ISE Service Pack" and "ISE IP Update". You can check the version by clicking Help-About in CORE Generator.
https://www.xilinx.com/support/download/index.htm
 
division verilog code

thnx a lot
i found my mistake
In the GENERATE OPTION i had clicked EDIF NETLIST
Now when i clicked NGC FILE it gave me right output
Now what to do next
Should i copy the NGC file in project and it will work
 

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