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initialize LFSR with seed

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soloktanjung

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coding of lfsr reseeding

hi,

i'm new to the DFT technique. hope anyone can help me. i've designed a
LFSR to test the 3 bit ALU. firstly, i'vr try to simulate the LFSR
using xilinx ise 9.2i, but no output signal is produced (only input
signal, which is reset and clock). i've read some books and articles,
tell that we need to initialize the LFSR by seeding with non-zero
value. how can we do this?

thanks in advance.
hairol
 

xnor lfsr seed

Which language are you using?

Here's an 18-bit LFSR in Verilog 2001. It initializes the register to 1:
Code: 
module top (clk, lfsr);
  input             clk;
  output reg [17:0] lfsr = 1;

  always @ (posedge clk)
    lfsr <= {lfsr, lfsr[17] ^ lfsr[10]};
endmodule
Another method: initialize the register to 0, and use XNOR feedback instead of XOR:
Code: 
module top (clk, lfsr);
  input             clk;
  output reg [17:0] lfsr = 0;

  always @ (posedge clk)
    lfsr <= {lfsr, lfsr[17] ~^ lfsr[10]};
endmodule
If you really need an external reset, here is synchronous reset:
Code: 
module top (clk, reset, lfsr);
  input             clk, reset;
  output reg [17:0] lfsr;

  always @ (posedge clk)
    lfsr <= reset ? 1 : {lfsr, lfsr[17] ^ lfsr[10]};
endmodule
I avoid asynchronous reset in FPGA design.
 
lsfr and seed

hi,

i'm sorry not mention that i used schematic entry xilinx ise 9.2i. can anyone shows me how to initialize the LFSR?

thanks in advance.
hairol
 

how to initialise lfsrs?

Schematic entry? Ok.

If you are using an SRL16 shift register primitive, you could attach an "INIT" attribute to the schematic symbol and set it to a non-zero value. That would initialize the register upon FPGA configuration. Or use XNOR feedback so the SRL16's default zero initialization works fine. However, an SRL16 doesn't provide any run-time reset input.

If you really need a reset input, you could use a general-purpose shift register with synchronous load such as an SR16RLED. Your reset input would synchronously load the initial value into the register. For asynchronous reset (usually not a good thing in FPGA), I suppose you could use something like an SR16CLED which has an asynch reset (for the reset-to-zero bits), perhaps combined with an FDCP flop (for the reset-to-one bit). Pretty messy. You could avoid the FDCP by using XNOR feedback and by resetting the register to 0. Any of these methods will consume significantly more FPGA resources than an SRL16.

Your ISE documentation include special Libraries Guides for schematic entry. They describe the various register types, and attributes such as INIT.

Most engineers find HDL much easier than schematic entry. Consider it!
 

lfsr for engineers

thanks a lot for your reply echo47.

this is my lfsr...

 

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