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What is the Length Of Diffusion effect?

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ajaytronic

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Can anybody explain what is LOD ( length of diffusion) efect correctly,
we face this problem in lower technology( 90 nm & below ).
How we decide matching pattering with considering LOD.

I just know about it is, we share dummies transistor to main one to combat its effect so its increases its LOD. Pls correct me if I am worng.

If anybody have related papers or document, pls share it.
 

length of diffusion lod

the trenches do mechanical stress on the MOS causing change in the MOS behavior according to how far it is from the trench so using dummy fingers decrease this effect cause u put the fingers far from the trench while using multipliers is better cause all the MOS will have the same stress (better matched)
 
lod sti

You can call this effect also STI (shallo trench isolation effect).
Due to this the current in the NMOS and PMOS transistors got effected. To avoide this effect in layout you have to avoide shearing the active regions for the matched pairs like current mirrors ,diff pairs... in otherwards try usig single or doubre fingure devices for the matching purpose. Do not use more than 2 or 3 fingures in the layout especially for the current mirrors and diff pairs.If u can maintain single finfures all the way you will get the extracted sims close to your schematics.
 
dummy transistors shared

Hi All,
Thanks for help.
can anybody explain LOD matcing.
lsuppose A is having 3 finger & B is having 4 finger with same W/L.
How we will match it.
Can we use shared dummies of minimum length ( allowed by technology) here.
 

Link is not work, Can you please share the link again. Thanks in advance !!!
 

These are good articles on Matching and WPE-LOD Effects.

Hope this Helps.

- - - Updated - - -

LOD-Length of Dissusion

Since because of Shrinking Technology node, the spacing becomes very compact.
We use STI instead of LOCOS in smaller Tech, Due to STI used the source or drain will get the stress from STI and thus the operation point varies.

In order to avoid LOD, dummy transistors are placed and shared with critical devices, so that the stress is not reached to critical devices.
Hope this Helps.

- - - Updated - - -

aomeen said:
Here is an excellent document about your requist:

www.ieee-cicc.org/06-8-6.pdf
Click to expand...

Some problem with link I suppose. It is not connecting, please resend the document by some other source.

It will be helpful for me and other folks.

Thank you,
Prashanth
 

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  • WPE_LOD_Paper.pdf
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    raki31

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Re: dummy transistors shared

ajaytronic said:
Hi All,
Thanks for help.
can anybody explain LOD matcing.
lsuppose A is having 3 finger & B is having 4 finger with same W/L.
How we will match it.
Can we use shared dummies of minimum length ( allowed by technology) here.
Click to expand...

Hi u can do in this way

A=3 B=4 D- dummys

D A B B D D

D B A A B D
 

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