Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help for $fwrite counter result

Status
Not open for further replies.

deqingTK

Newbie level 3
Newbie level 3
Joined
Dec 26, 2007
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,315
Recently i have being doing a project in school, and i have being stuck for doing a program using verilog hdl.

i need to write a program using verilog to produce a notepad file with a output of the following: 1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1

So simply, a verilog program to produce 5 rows and columns of 1s.

I am new to verilog, so i dun exactly sure where do i start.

So.. help? anyone?
 

That sounds like an exercise in learning file I/O system tasks.
I don't understand what you mean by "counter result".
Here's one approach. It simply opens a file, writes some text, then closes it:
Code:
module test;
  integer fd, n;

  initial begin
    fd = $fopen("file.txt", "w");
    for (n=0; n<5; n=n+1)
      $fwrite(fd, "1 1 1 1 1\n");
    $fclose(fd);
  end
endmodule
 

    deqingTK

    Points: 2
    Helpful Answer Positive Rating
Thanks!

It helped alot! =)

That code above let me have a clearer understanding of $fopen and $fwrite.

The counter result, hmm, actually what i meant was that i was intending to use a counter, and display the outcome of the counter into a .txt file. But i dont really know what should i call it. =/

I realise there is another approach by using a clock, reset, row counter and column counter. The number of rows and column i may need to do comes in hundreds and thousands, and needed a reset function.

I am not very sure with this. I thought the program should be something like this shown below.

always@(posedge clk)
begin


if(col_cnt>5)
begin

col_cnt<=col_cnt+1;
$fwrite(file_out,"%d %d %d %d %d ",din);

end
else

col_cnt<=0;



end

always @(posedge clk1)
begin
clk<=~clk;
end

always@(posedge clk1)
begin

if(row>5)
row_cnt<=row_cnt+1;
$fwrite(file_out,"\n");
else
begin

row_cnt<=0;
end
end

endmodule

But i am not very sure about the clock thingy, but its pretty much required in my project. Hope somebody can kindly help me and guide me thru. Thanks!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top