Problem with Altium Designer

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To carry over the constraints information, you merge it with the existing PADS constraints file. An excerpt from PADS help files is included in the attached ZIP file.

To save design rules for future projects, you create a startup file. An excerpt from PADS help files is included in the attached ZIP file.

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- Is CAM350 able to do antenna effect checks, or I must use Camtastic?
- After checking and editing design file in CAM350, and exporting to ASC file, PADS was unable to show the changes in file! It just shows the original design!?
- I was hopeful to generate layer stack-up info in Blueprint and import it back to PADS, it is done but the result was poor. Do I need to learn AutoCAD to finish design with proper fabrication note? Or another documentation tools exist?
- The constraints now are exported to PADS. I want to choose one tool and start to build library or convert existing libs. It looks that OrCAD is not suitable tool for PCB design especially when dealing with high speed PCBs. I am wondering is DxDesigner able to communicate properly (forward & backward) with Allegro?

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In CAM350 to check for net antennas you use Analysis>Nets>Check Nets. There is a dialog that pops up with a check box for net antennas.

I'm not sure what you did wrong. If you make changes in CAM350, and then export the file to a PADS format, you should see the results of your changes. Try saving a CAM file from CAM350 before you export. Perhaps the act of saving the file will ensure your changes are properly recorded.

Most PADS users develop their own standard sheet with fabricaiton notes and a stackup diagram that they draw using PADS layout tools. They reuse that sheet from project-to-project.

No, DxDesigner will not communicate completely in both directions with Allegro. You can't cross probe, you can't preview decals, and only certain constraints are passed to Allegro when the netlist is imported. You need to set up a custom cfg file to properly pass attributes/properties to Allegro. There are third party tools such as PCBNavigator that offer constraints editing and cross probing from DxDesigner to Allegro.

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Also make sure that cross-probing and cross-selection are turned off.

JD

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As a main question befor switching to it: Is DxDesigner dependable?

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I don't know what you mean by "dependable". It's a mature package, originally published by Innoveda in 2001 before Mentor bought the company in 2002.

It has a steep learning curve, and takes more effort to develop library components than many other packages. As schematic capture programs go, I would rate it as average.

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Sorry, I know that the question looks silly,
But I want to know any problem, weakness or inconsistency. Understanding this problem before starting the project is valuable; finding this problem in the middle of project is very costly.
Actually I want to know which schematic tool do you prefer for high speed and complex boards?

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Any help?

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The first thing to recognize about schematic capture is that it has nothing to do with high speed design or board complexity. High speed complex design is done in the PCB layout editor. The schematic capture software is only a means of documenting the circiut connectivity, and passing that connectivity to a netlist.

There are obviously other features that can be incorporated into a schematic editor. Such as the ability to pass design directives through to the PCB editor; however, those things don't show on a finished schematic document. Furthermore, they are just as easily established in PCB design rules from the layout editor, or a constraint editor (depending on which software you use).

If you are going to rely on the extras in a schematic editor to communicate with the PCB editor, you have no choice but to use a closely integrated EDA package. You're not going to be able to pick and choose which schematic editor to use with which PCB layout editor.

From the standpoint of stability and ease of use, Altium Designer is my favorite. From the standpoint of most thorough design specification starting at the schematic capture level, Cadence Concept HDL used with Allegro and Specctraquest is the most comprehesive design flow. It is also one of the most expensive and difficult to master EDA packages.

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Dear House_Cat:
In some baord (for example mothrboards) and around the mounting holes we see some other six or eight small holes, what is the mean for this small holes?

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Those small holes are usually grounding vias to connect the pads on the top and bottom of the board to the ground sheild plane. When you put a screw through the hole, the ground shield plane is then mechanically connected to the external chassis to which the board is mounted.

This sort of grounding needs to be done carefully. Connecting just any ground reference plane to an external chassis could cause noise to be coupled into the board.

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I am wondering why the plated hole, without those small hole, do not work the grounding job?

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A single plated hole would work. However, having multiple vias decreases the inductance of the overall structure. In the case of a shielding connection, you want to avoid having series impedance at the connection.

Remember - all plated holes in a PCB have inductance and capacitance. When working with high frequencies, those sources of reactance become of concern. At lower frequencies, we tend to ignore the small values presented by a thru-hole via or pad. At higher frequencies, it's best not to ignore them.

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I suggest that a chain of via around the boundry of high-speed boards has the same effect. Those via always has the closed shape.

In PADS, is this true to say that all vias are soldermask covered on both side?

In AD, is it possible to force it to place new components into the placed rooms? Normally new components are place all over each other on right hand side of board!

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The chain of vias around the outside edge of the board is for a different purpose. They form a "fence" to suppress emissions from between the plane layers of the board. In that case, the planes act as the top and bottom walls of an open resonant cavity that can radiate. The "fence" vias close off the cavity and contain the signal that could cause your product to fail EMC testing.

The vias in PADS have soldermask if that is what you have set up in Setup->Padstacks->Via. If you don't want soldermask, you leave it out in the padstack setup.

In AD, if you look at Project Options->Class Generation you will see a column for Component Classes. There are check boxes in that column to allow you to generate rooms for components when the schematic is compiled. You can then move the room on the PCB and the components will move with it.

Additionally, you can toggle the Cross Selection mode on the Tools menu in both the Schematic Editor and the PCB Editor. When you select a group of components on the schematic, they will automatically be selected on the PCB as well. You can then move the selected components (move selection; shortcut MS) as a block. You could also make a new room around the selected components using Design->Rooms->Create Rectangle Room from Selected Components. Then you can move the new room where you want it with the components in it.

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How I can be sure that my board will pass the EMC tests? What is EMI and is it related to EMC? Is there any tool to simulate this feature of routed board? Electromagnetic problems always difficult in nature, there must be an instruction set for PCB designer to avoid EMC problem!? What AD could do for these sorts of tests?

Regarding room generation, actually I am using it, and it is default setting in AD. It is working for fist time, but problem will arise after adding new components. Suppose that I have added a resistor to a page and I want it to be transferred into the room which is related to its schematic page. When we have many new components, this feature might be very useful!

In my last board, I had drill offset problem, it is not sever but it is visible and it my cause broken nets. Is teardrop useful to mitigate this problem? Is it common to add teardrop in multilayer boards?

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EMC is "Electromagnetic Compatibility". EMI is "Electromagnetic Interference". Both of them are controlled by the way you design your board.

EMI is generally considered to be the precautions you take to ensure that your sensitive signals will not be distorted by interference from outside the board, or from other signals on the board.

EMC encompasses the precautions you take with your design to ensure that your circuit will not radiate interference. There are design standards that set requirements for your board to meet in order to pass EMC testing. Passing EMC testing is required in some parts of the world in order for you to market your product. There are several good books on the subject of designing for EMC. One of my favorites is "Printed Circuit Board Design Techniques for EMC Compliance", by Mark Montrose. AD will not automatically test for design faults that could lead to EMC problems. There are a few programs that claim to be able to do design rule checks to prevent EMC; one of them is **broken link removed**

Teardrops are used to mechanically reinforce pads in places where there are large components anchored to the board by the pads. Flexing of the board by the large components could break the joint where the pad meets the trace, so a teardrop is added to mechanically strengthen the joint between the annulus and the trace. You will hear some people claim that teardrops are used to prevent sudden changes in impedance between pads and traces - that's nonsense. You could use teardrops in the case you experienced with drill offset; however, the usual way to control that situation is to simply use a larger annulus on your pads and vias.

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I am trrying to find out more about Zuken CADSTAR, STARCAD website is not strigh forward and it is cumbersome! By its file size(<100MB) it must be a beginer!
If you want to compare it with AD, PADS, and Allegro, where is the place for it?

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I haven't used Cadstar since it was Racal-Redac many years ago. I don't know what the current version of Cadstar or CR-5000 has to offer compared with other EDA software. I do know that some divisions of large companies like Philips, Sony, and Mitsubishi have used Cadstar.

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Something is wrong with my AD, after closing a project(AD without any loaded project) it is still using 800M of memory!!! Is it acceptable that AD framework consume such a large amount of memory?