Problems with 8 bit DDS as it stops "half way"

anyone please help .
tell me the step to come out with DDS
120 MHZ
8 bit

please help

modelsim display sine wave

Are you using a Xilinx device? Which one?

Try the "DDS Compiler" or "Direct Digital Synthesizer" cores included with Xilinx ISE CORE Generator.

Or build your own DDS. Feed a frequency constant into an ordinary arithmetic accumulator. Connect the accumulator output to the address inputs of a sinewave lookup table ROM. The ROM output is your digital sinewave.

dds compiler example xilinx

Xilinx

okies i got my 8bit
but i don know what happen it only show me the wave half way . from 0000 to 0101001
the rest nothing ....
i don know why . any one
help~~ please

dds+xilinx+example

What software are you using to display the wave? If it defaults to unsigned value display, then you should configure it to display signed values (both positive and negative). In ModelSim, right-click the signal's name in the wave window, select Properties, and then explore the various options.

dds modelsim

err i got a wave and but it only showing iit half way

dds compiler

err i got my 8 bit signal half way .
it stop and all the way become red line .

there's my test banch

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS


COMPONENT dds
PORT(
clk : IN STD_LOGIC;
sclr : STD_LOGIC;
SINE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

SIGNAL clk : std_logic:='1';
SIGNAL SINE : std_logic_vector(7 downto 0);
SIGNAL sclr : std_logic;


BEGIN


uut: dds PORT MAP(

sclr=>sclr,
clk=>clk,
SINE=>SINE
);
sclr <= '1','0' after 0.1 ns;


tb : PROCESS
BEGIN

clk <= not clk after 1 ns;
wait for 1 ns;
END PROCESS tb;


END;

anyone help ~ please

sine table vhdl dds vhd

What is the name of the software that's showing you the incorrect waveform?

Can you show us a screen image of the malfunction you see?
Have you configured your waveform viewer to show signed (positive and negative) values?

In your VHDL testbench, where is your "DDS" component? If it's a core, which one did you use, and what parameters did you specify to create it?

Your testbench simulates fine in ModelSim 6.3c. I generated an 8-bit DDS core using Xilinx coregen and "DDS Compiler 2.0". The clock is 500 MHz, the sinewave is 120 MHz. Here's a screen image. The vertical scale on the "sine" signal is from -128 to +127:

dds help

MOdelSim XE III/Starter 6.1e - Custom Xilinx
i using Direct Digital Synthesizer 5.0
this is what i get sad

modelsim dds

this is what i got

quadrature oscillator using dds in xilinx

err how to check whether the vertical scale on the "sine" signal is from -128 to +127 .
and is there a way you can shift the whole "sine" singal to upper the Zero like moving the whole sine above zero

example dds simulation+modelsim

Wow, I didn't expect to see that!

Your 'sine' signal is displayed as simple binary, so it has no vertical scale. Earlier, when you said it was displaying only "half way", I thought you meant in the vertical direction, not in the horizontal direction. My comments about signed and unsigned therefore don't apply.

The Xilinx DDS core shouldn't run at all during the first 100ns, because the FPGA's global reset signal is active. Your signals are somehow active before that time, and then become undefined after a few clock cycles. Also, your signals appear to change on the *negative* edge of the clock instead of the positive edge. Very strange!

Your screen snapshot shows only the first 35ns. Does anything interesting happen after 100ns?

To display the "sine" signal as an analog waveform (like my snapshot), right-click the signal name, click Properties, change the radix to decimal, change the format to analog, change the offset to 128, change the scale to 0.5, and change the height to 128.

I've never seen a malfunction like your display. I don't know what's wrong. Maybe it's an installation/configuration problem between ISE and ModelSim. Be sure you have installed all the available ISE and IP service packs. Which version of Xilinx ISE are you using?

Your screen snapshot looks like a pre-route simulation. Is that correct, or is it a post-route simulation? If it's a post-route simulation, then I don't think any Xilinx device can run the DDS core at 500 MHz, so maybe that's what's wrong. Does ModelSim give you any timing warning messages?

Maybe you could zip up all your project files and upload them somewhere, so someone could try to figure out what's going wrong.

dds compiler v2.0 simulation modelsim

err nothing after 100ns is all the red line
errr what you see. is all i have
don know why when i run 9 or 10 bit nothing wrong
you can go all the way to 100ns but . when i try on 8bit . error . anyone know how to solve

how to execute 4 dds synthesizers for dds project

When I use your dds.vhd file, I now see the malfunction.

Your 'sclr' pulse is too short. It isn't providing good setup time before the clock. I lengthened the pulse, and the simulation now runs fine with your dds.vhd file. However, it is on the verge of failing due to high clock frequency. If I slightly increasing the clock frequency, I see the DDS output update rate drop in half - it is probably missing every other clock cycle.

Remember that 500 MHz is probably too fast for this DDS core in any Xilinx device.

dds compiler ver 3.0 + ise

'sclr' pulse is too short ? It isn't providing good setup time before the clock. how do you lengthened the pulse?

err so you mean under my DDS setting .

i got to set the DDS Clock Rate lower ?
but i set it 300 MHZ or 250 is still show the same thing =(

is there other setting

ise dds core

You wrote the testbench that generates the sclr pulse, so you should know how to change it!
Here's your statement that sets the sclr pulse width:
sclr <= '1','0' after 1 ns;

The simulation malfunctions because sclr has bad setup time, not because the clock is too fast.
However, the simulation is just barely working at 500 MHz. It malfunctions at 501 MHz.

The core probably won't work in an FPGA at 500 MHz.

xilinx dds sclr

thanks for the help ^^
im not very good in VHDL

what sclr you think is the best ?



uut: dds PORT MAP(
sclr=>sclr,
clk=>clk,
SINE=>SINE
);

sclr <= '1','0' after 1 ns;


tb : PROCESS
BEGIN

clk <= not clk after 1 ns;
wait for 1 ns;

END PROCESS tb;


END;

help me please
i still trying out

dds sclr

Try changing the sclr pulse width from 1ns to 3ns, so it is high both before and after the rising edge of the clock.
You can zoom in on the ModelSim wave display to see the relationship between clk and sclr.

coregen dds quadrature problem

i was ask to shift the whole wave above the zero . can that be done ??

xilinx dds compiler example

If you simply wish to adjust the appearance of the wave in ModelSim, see my earlier message about setting the radix, format, offset, etc. That configures the wave's vertical offset and amplitude to appear like my ddswave.gif snapshot.

I have version 6.3d of ModelSim, so my menu arrangements and parameter names may be different from yours. ModelSim rearranged them around version 6.3.

xilinx dds testbench

err but i like to know if i can move 128 to -91 to both postive like 128 to 91