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Using shift register and MUXF7 to realize dual-Clock FIFO

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EDA_hg81

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dual clock fifo +xilinx

Can I use MUXF7 as a switch to select one of two clocks for realizing shift register based dual-clock FIFO?

Thanks.
 

I assume you are referring to a Xilinx FPGA. I'm not clear exactly what you are building, but if you really need to switch between two clocks without glitches, try the BUFGMUX (if your FPGA provides it) instead of an ordinary mux such as MUXF7.

If possible, try to design synchronous logic that doesn't require gating or switching clocks.
 

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    EDA_hg81

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Re: Using shift register and MUXF7 to realize dual-Clock FIF

Thanks.

Just for building a dual clock FIFO.

But BRAM based dual clock FIFO is big, I only need 16 byte deep.
 

Re: Using shift register and MUXF7 to realize dual-Clock FIF

EDA_hg81 said:
Thanks.

Just for building a dual clock FIFO.

But BRAM based dual clock FIFO is big, I only need 16 byte deep.
Click to expand...

Hi,

Instead of BRAM, use Distributed RAM based FIFO. It is synthesized as LUT only and does not consume any of BRAM on FPGA chip.

If you are using Xilinx FPGA, please refer XILINX Core Generator IP CORE guide.

Enjoy!!!
 

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