Problem with Altium Designer

pads file buried resistors

I am intersted in PCB design contract steps and input / output info.
What info do you expect from your customer at start? Complete schematic, with specified footprints? Or schematic is also the duty of PCB designer? After finishing can customer expect a copy of orginal PCB files, or he/she will receive just PDF or Gerber files?

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Every job is different. Some customers provide a rough (hand drawn) schematic, mechanical details (enclosure dimensions, mounting hole sizes and locations, clearances, etc.), design notes regarding critical signal paths, a BOM with enough information to gather component data sheets, and any other details that would affect the project completion time. These customers may want a smooth schematic, a board design file, and project documentation as the final output.

Other customers want a complete product design. All they provide is the desired input and output, plus any mechanical limitations they would like to meet.

Still other customers provide a smooth schematic in a format that I can import or open in my EDA software, and other details in nearly finished format. All they really want is a board design.

What the customer gets at the end of the project depends on how much they want to pay, and what has been agreed upon at the begining of the project. If the customer has provided a complete schematic, and all of the design details, they own the whole project. I quote them a price for the smooth schematic output, the Gerber files, and the design documentation.

If the customer wants me to do the entire product design, I quote them a price for the rights to the design, and a lower price if I maintain the rights to the design. If I keep the design rights, the customer will not receive Gerber or EDA files - they will only get PDF documentation. If the customer pays for the design rights, they get anything they want.

The important thing when talking with a customer about a job, is to determine what they expect as a final output from you. You should not give away your time. Things like printed documentation take time and materials just like laying out a board. If you are expected to provide a full set of printed documentation and the electronic files, you should factor that time into your quote. If the customer complains about the cost, you can offer to cut the cost by reducing the extras being requested.

The hardest part of reaching agreement on cost is accounting for customer requested changes. Every change to a schematic, or the design requirements, adds time to your effort - time is what you are charging for. Your contract with the customer should include a paragraph on how cost will be determined if design changes are made at certain points during the progress of the project. Cost should go up if the changes are made after the PCB is laid out, for example, because that will add more time than changes made while the schematic is being drawn.

origin ipc2221

On AD it is possible to set plane pull back also we can set plane seperation by a line thckness. I was looking for the same feature on PADS, but it is missing!?

buried vias fabrication notes

In PADS the only setting you have is on the 'Tools>Options>Split/Mixed Plane' tab for "Gap". When you auto create a plane, the gap setting makes the plane smaller than the board outline. PADS doesn't allow the degree of control found in Altium Designer for pullbacks and split plane separation distances.

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Is downstream and their products CAM350 and blueprint parts of Mentor Graphics?

As a PCB designer, how much do I have to be familiar with CAM tools?

On AD and fabrication output generation for both gerber files and drill drawing, mm and inch option exist. Also user can choose the precision. Which unit system is better? If my design is metric and I chose inch in mask generation, what problem may arise? Also how much precision is enough, .000, .00, .0?

In urgent situations and for sample board we even use hot air tool to solder component or may fix its problem. I am wondering is any method exists for BGA device manual soldering?

In AD library many 0603 or 0805 exist. Can we expect all capacitor, resistor and inductor with same 805 or 603 feature fit to same footprint? You may ask why I am asking it! Actually I faced a problem; inductors for example with 0805 codes do not fit to 0805 general footprint.

In order to be sure about pick and place machine operation, how far 603 and 805 res/cap must be placed?

Both 603/805/402 footprints usually have a rectangular in silk-screen layer around them! Without this box we can place them close to each other and reach much more density in our designs, but removing this box is not common! I saw many motherboards for PC and Industrial PC and also many other boards, most of them use this box! What is the reason for using this box? Is it related to assembly issues?

In mixed PTH and SMD designs (PC motherboard for example), which soldering method is suitable? Is reflow method applicable for this sort of designs?

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Downstream Technologies is a Mentor Graphics "Open Door" Partner Company. Mentor doesn't own them, but they have an agreement to make CAM350 and Blueprint easy to work with from PADS. There is builtin translation software to allow CAM350 and Blueprint to translate Mentor EDA formats.

The CAM output of your PCB is how your boards are made. It isn't essential that you know a great deal about CAM. However, the more you know about a CAM editor, the more you can understand and control the fabrication process. There are some checks of Gerber data that can best be done from a CAM editor - such as antenna checks, and silkscreen over pads.

Generally, you don't want to mix measurement units for two reasons. One is rounding errors that occur when you change your base units. The other is that your fab may become confused if half of your CAM files are in one set of units and the rest is in another. Be consistent - pick a set of units and stick with it. The precision depends on what you are doing. Some boards will be fine with 2.3 (Imperial) precision, and for others with fine pitch components you'll want at least 2.4 (Imperial).

Reflow ovens or hot plates are used for BGA. I don't know of any reliable hand soldering technique for BGA.

Although 0603 and 0805 footprints should be standard, they are not. Different manufacturers may vary slightly from the standard IPC footprint. It is best to check the data sheets for the specific components you are going to use. In general, resistors can use a slightly smaller pad than capacitors, and capacitors use a slightly smaller pad than inductors. There are exceptions, so check the data sheets. That is why there are several footprints in the libraries with the same size lable. To further complicate the matter, the IPC specifications allow for three different sizes for each footprint made to their requirements. There is "Least", "Nominal", and "Most" for each footprint. The "Least" pad size is for exceptionally dense boards to allow the most components per given area. "Nominal" is the average size pad for a normal density board. "Most" is the largest pad for hand soldering and low density layouts.

The spacing between components for pick and place is a function of the equipment used by your assembly house, and the soldering method that will be used. IPC7351A gives minimum courtyard excess dimensions suitable for reflow soldering. Wave soldering requires a bit more spacing between components to avoid solder thieving. Give your assembly house a call and ask about their limitations. Additionally, some assemblers with older equipment can only place components with rotations that are multiples of 90deg. Newer equipment can handle any angle of rotation.

The box you see around components is the "courtyard". It is intended to be a boundary for handling of components, soldering, and testing. It gives a visual indication for minimum spacing between components.

In mixed technolgy designs, the SMT components are usually reflow soldered first, then the thru-hole components are hand soldered. If the board is designed with cheap assembly in mind, all of the SMT components can be placed on one side for reflow soldering, and the other side can be wave soldered for the thru-hole components.

ipc-a-600g pdf

Is "courtyard" required for BGA devices?
What is use of unions and snippets in AD? what is difference between them? Are they similar to reuse in PADS?
Do you use rooms in your board placement?

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A courtyard is never "required", but it gives you a visual indication of the actual size considerations for the component when you are placing it. I like having a courtyard for all my PCB footprints.

A union allows you to work with a group of primitives as if they are one component. You can tie traces and components together, and then move them, select them, or copy them as if they were a single block. A snippet is a block of schematic or PCB that can be stored permanently and then recalled to be used over and over again. It's a library of circuit blocks that you can reuse for frequently used configurations.

For high part count boards I do use rooms. It makes placement easier, and I can relocate rooms of components faster when doing initial part placement.

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Can we lock our design in AD? suppose that you want to give your customer a copy of design, may be as part of your contract, but you do not want them to be able to extract library.
This feature exist in Allegro, I can add a password to my .brd file to portect its data from being extracted!

Also can we export placement info of PCB in AD? It is useful for board replacement, or use placement info in other tools.

orcad offsheet references

No, you can't lock a design to prevent editing by another person who also has AD. Your PCBDoc file can be opened and edited by anyone with a full copy of AD. There is a free viewer edition of AD which can only be used for viewing, but the file itself can't be locked.

The placement information is contained in the pick and place file that can be generated from AD. It can be generated from an "OutJob" file, or you can create it from the menu "File>Assembly Outputs>Generates Pick and Place Files".

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AD in auto-router mode do not recognize diff-pair and delay tuned or length matched constraint on nets! How we can fix it?

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The Situs autorouter in AD is a low-end router and does not have the capability to automatically route differential pairs or matched length traces. Those functions are intended to be done interactively (manually) before the autorouter is run. The design rules for differential traces and matched length traces are intended to be used with the interactive tools to make it easier for you to place the critical traces.

Once the critical traces are placed interactively, you are supposed to lock them to keep the autorouter from ripping them up, and then run the autorouter for the non-critical traces.

There's a table starting on page 23 of "TR0116 Design Rules Reference.pdf" that tells you what rules will be used by the autorouter.

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I was looking in AD for stackup/line simulator like hyperlynx, Do AD have capability?

In some designs, specialy memory based board, designer prefer to make clock line longer than other, what is for?

Is AD able to put intersheet reference like OrCAD for off-page connectors? It does it for ports!

altium unmatched component objects

In PCI and PCIe cards special cuts are required, is board outline enough for specifying this information or I must provide detail with other mean? My PCB fab was talking about CNC programming!

additional mechanical layer altium

AD does not have a line or stackup simulator like Hyperlynx.

The length of the clock line is sometimes varied to control timing skew. I'd have to see the specific design to tell you exactly why it was done in a particular case.

No, sheet references are not provided for off-page connectors. It's supposed to be a feature that is being added in the future.

Your fab can do their CNC programming from a Gerber file of the board outline to route irregular board shapes and cutouts. I've never had to provide anything more than the Gerber file, and notes for any special instructions (such as tolerances).

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I saw clock line tuning mostly for memory based design, especially for DDR SDRAM. In other design which targeting ZBT SRAM, designer was asking the PCB designer to make clock line about 500MIL longer that data line!

To fix the intersheet ref. problem I was using port instead of off-page connectors, even AD do complains and give some error marker, but the netlist and connectivity is complete. If you want to be sure about connectivity, which steps and settings are required? It seems to me that OrCAD has better DRC and connectivity checks!

Without line and stack up simulator, stack-up planning is very difficult specially for impedance critical designs, which tool do you prefer: Hyperlynx or SpectraQuest (AllgeoSI in SPB16.0). Is there any free or low cost tool?

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The extra 500mils on the clock line was probably to introduce a clock delay to allow the data to settle before read/write. Remember that the data is read or written by the clock signal edge. If the data is asserted a little earlier, you can be sure that it has settled before the edge arrives.

The connectivity depends on whether you are using a flat or hierarchical schematic. You specify the scope of nets in the Project Options, and wheter or not ports automatically assign nets. If your schematic is flat, simple net names will connect across sheets. Off sheet connectors are used to connect nets
across multiple schematic sheets that are descended from the same parent sheet symbol.

For impedance critical designs I use a field solver to determine the stackup. Tools such as Hyperlynx are just not accurate enough. I'm not aware of any free or cheap tool that will do a good job. However, you can get short term licenses from Polar Instruments that don't cost too much ( https://www.polarinstruments.com/ ). Between Hyperlynx and Specctraquest, Hyperlynx is the easiest to use and the least expensive. Altium Designer will output a file in Hyperlynx format.

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In the process of developing electronic products, do board designer involve in board functionality test?

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Board designers do not usually get involved with functional test. Application engineers and test engineers do the test programming and analysis. They are separate specialty areas.

altium directx problem

In DxDesigner files, a file with .CNS ext. exist which is the constraint database. ePlanner and XTK, and ... , can generate or update it. The content is PCB design rules.

Can I use it in PADS, or it is for other toold in ePD suite? If so how I can apply it to PADS? I have searched all menus and submenus for how to apply it!

Can we export constraint of PADS into a file for backup or reuse? In OrCAD+PADS conbiniation, with each netlist import, constraints dissappear and we have to set them up again!