Kuller
Junior Member level 1
multicore fpga spartan
Hi,
I am having some trouble with the Xilinx implementation. The thing is that I have two different projects that fits directly into the same FPGA sharing the clock. One of them can run up to 150 MHz and the other one up to 70 MHz.
The problem is if I constraint the clock for 150 MHz it doesnt let me to implement the design as the slow core has a path delay bigger than 6 ns. I dont really care about this as I know that it is not going to be used at more than 70 MHz but the implementatin fails.
My configuration is: (same constraint for both clocks, doesnt work)
IOB->DCM->core1
|-> core2
I have tried too: (same as before)
IOB->DCM1->core1
|-> DCM2->core2
And:
IOB->DCM1->core1 ( ologic problem but I can get 2 different clock nets)
|->DDR FF->DCM2->core2
I tried to put a from, to constraint ( It didnt work )
Is there anyway to split 1 clock into two fully independent clocks?
I am really stuck at this moment :/
Thanks
Hi,
I am having some trouble with the Xilinx implementation. The thing is that I have two different projects that fits directly into the same FPGA sharing the clock. One of them can run up to 150 MHz and the other one up to 70 MHz.
The problem is if I constraint the clock for 150 MHz it doesnt let me to implement the design as the slow core has a path delay bigger than 6 ns. I dont really care about this as I know that it is not going to be used at more than 70 MHz but the implementatin fails.
My configuration is: (same constraint for both clocks, doesnt work)
IOB->DCM->core1
|-> core2
I have tried too: (same as before)
IOB->DCM1->core1
|-> DCM2->core2
And:
IOB->DCM1->core1 ( ologic problem but I can get 2 different clock nets)
|->DDR FF->DCM2->core2
I tried to put a from, to constraint ( It didnt work )
Is there anyway to split 1 clock into two fully independent clocks?
I am really stuck at this moment :/
Thanks