perylee_sh
Newbie level 6
STI stress effect is described by two geometric pamameters SA and SB.
The question is: post simulation results show that these two parammeter
can greatly shift the electrical performance of mos transistor, so, device
performance is impacted by layout features. How can I mimimize this in
layout design?
Compare pre-sim and post-sim result, different SA and SB can cause Isat
change greatly.
Hope you can help me.
THX
The question is: post simulation results show that these two parammeter
can greatly shift the electrical performance of mos transistor, so, device
performance is impacted by layout features. How can I mimimize this in
layout design?
Compare pre-sim and post-sim result, different SA and SB can cause Isat
change greatly.
Hope you can help me.
THX