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Design Mismatch after synthesis

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tok47

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Hi ALL,


I am a newbie in digital design. This is the first time I use synthesis tools. So, hopelly my question is not a stupid question.

In my design, I am using a combination logic plus latch to latch a data. It works pretty good in my verilog simulation. But, the simulation that I use the design after I synthesis, it not working as what I get in verilog simulation. The latching data keep toggling.

Previously, I was using a flip flop in my design. But, due to a delay at the DATA side, so I always getting a wrong latching data.

Is that is a common case where the circuit after synthesis is not cross match the verilog behavioral?

Thanks


rdgs
YY
 

synthesis is pretty reliable now, unless your coding style is really poor.

chances are your gate level simulation setup is not correct, it may be either reset or time step related.
 

Is there any golden coding style that always can make sure the clock is toggle after the data ready for a flip-flop?
 

were there any setupt/hold time violations after synthesis ?
i
 

hi,
1. first sing formality or conformal to prove rtl vs. netlist is ok
2. not using sdf to do netlist simulation
 

Hi, This is a common behavior. The RTL simulation is a 0-delay simulation, whereas netlist simulation is a delayed simulation. So when delay comes into picture these kind of probs are observed. To avoid them u need to ensure that these probs dosent arises by design, i.e. in RTL. Modify your RTL(preferable a latch to latch the correct data even if there is some delay in the signal path). This will solve your problem.
 
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