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Why this Verilog coding used in testbench is wrong?

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lostin_eda

lostin_eda

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About verilog coding

Hey, the following statement which is used in testbench, and i think it is wrong, right? and tell me why it is wrong thanks for your help

always @ ( a or b or c)
begin
if ( a)
begin
@ (posedge clock);
e = b;
end
else
begin
# 10 ;
e =c ;
end
end
 

Re: About verilog coding

@ (posedge clock);
 

Re: About verilog coding

kanagavel_docs said:
Hi,

Plese describe your requirement...

Kanags
Click to expand...

I just want to know that whether "@ (posedge clock )" could be added in the statement
if "a" is true "e" will be assigned with "b" after the rising edge of clock comes, but if "a" or "b" or "c" changed when waiting for the rising edge of clock?
 

Re: About verilog coding

Hi,

This always block is sensitive to a, b, c inputs only. So tough to capture the rising edge of clock. If the clock rise and any one of the input change happens at the same time only the execution will move from this statement. So, add clock in the sensitive list and try.

Regards,
Kanags
 

    lostin_eda

    lostin_eda

    Points: 2
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About verilog coding

Thank you all
 

About verilog coding

i have run this code in ISE9.2i, but there is no error checked ,except no changes on signal.
 

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