jason_tian
Junior Member level 2
Hi,everyone
I'd like to make a 1/4 devider ('osc'/40KHz---->'clk'/10KHz) by the code as follows:
reg[9:1] devider;
always @(posedge osc)
if(devider>=2) begin clk<=~clk;devider<=1;end
else devider<=devider+1;
the waveform of 'clk' jitters, sometimes the 'clk' raises or falls on a wrong edge of 'osc'.please refer to the picture.
EPM240T is used.
Added after 3 minutes:
[/img]
I'd like to make a 1/4 devider ('osc'/40KHz---->'clk'/10KHz) by the code as follows:
reg[9:1] devider;
always @(posedge osc)
if(devider>=2) begin clk<=~clk;devider<=1;end
else devider<=devider+1;
the waveform of 'clk' jitters, sometimes the 'clk' raises or falls on a wrong edge of 'osc'.please refer to the picture.
EPM240T is used.
Added after 3 minutes: