A few sigma delta design questions...

s pavan r pandarinathan

I have simulated a 3rd order CT sigma delta ADC in simulink...now I want to build it in cadence using spectre.. 0.3u technology
The main blocks are:
1)Integrator for which I will be using an RC-active opamp integrator

Now how should I go about its specs??The gain,bandwidth etc

2)Quantizer...I have no idea abt this...any quantizer ckt will be helpful

3)Adder blocks...shud I used some digital summer or go with an opamp adder

4)DAC...I want to use a NRZ DAC...can anyone provide a good ckt...I am currently working on it rt now...

Thanks...any help wud be greatly appreciated

1.The first integrator is the most important block. The unity gain frequency for a discrete time sigma delta mod must be at least 3-4 times the switching frequency.
2. A comparator works as a 1 bit quantizer.
3. The integrator virtual ground node can be utilized for summing. A feedback resistor from output will do the summer.
4. For a 1-bit quantized output, simplest way is to switch the feedback voltage between +Vref and -Vref as the latched comparator output toggles. (The output of the comparator has to be latched).

lavitaebelle said:

1.The first integrator is the most important block. The unity gain frequency for a discrete time sigma delta mod must be at least 3-4 times the switching frequency.
2. A comparator works as a 1 bit quantizer.
3. The integrator virtual ground node can be utilized for summing. A feedback resistor from output will do the summer.
4. For a 1-bit quantized output, simplest way is to switch the feedback voltage between +Vref and -Vref as the latched comparator output toggles. (The output of the comparator has to be latched).

Click to expand...

Thanks for the reply

Yes,the comparator is a 1-bit quantizer...but I need a 4-bit quantizer...any idea how I can get that...
Abt the summer,I think I will do wat u said...use the opamp summer using FB resistor...

Now,abt the integrator...my sampling rate is very high...640MHz to be specific and mine is a CT and not DT modulator...will the specs be te same...u mentioned UGfreq...wat abt its gain bandwidth product...and I think I should design the integrators for the same output swings I got in the system level simulation...

Finally abt the DAC...I need a ckt...

Anyone with info on these,plz reply.
Thanks.

I dint see your post properly. Assumed its a DT modulator. For a continuous time modulator, the integrator bandwidth is much lower, about 0.7 to 1.3 times the sampling rate. So you need UGfreq about 640 MHz.
Simplest 4-bit quantizer would be a 4 bit flash ADC.
The feedback DAC needs to be carefully designed for a CT modulator. The DAC response is part of the loop filter response. You need a 4 bit DAC instead of a one bit DAC.
There's a nice paper just published at European Solid state Circuits conference which talks about multi bit quantizer CT sigma delta ADC.
S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, "A 90 µW 15 bit Σ-Δ for digital audio'', IEEE Proc. European Solid State Circuits Conference, 2007, pp. 198-201.
Let me know if you cant find it.

Once again thanks for the reply...I couldnt find the paper...If you could please upload it,I wud be grateful to you.

Ok,now you mentioned that its UGF shud be abt 640MHz...wat abt its Gain-bandwidth product..bandwidth,gain etc...

My specs from my simulations are:

Swings are +/- 0.2,0.8,1.2V resp at the outputs of the three integrators...shudnt I design my opamps for these output swings...and wat abt the DC level of the opamp output...shudnt we make it zero if we want it to match with the system level output

My +/-Vref is +/-1.2V

Quantizer is 4-bit as I mentioned

I got a peak snr of about 70dB

Here is the architecture I am implementing...

[img=http://img150.imageshack.us/img150/2509/thirdorderctko5.th.jpg]