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diode in CMOS technology

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pvreddy

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nw/psub diode

Can anybody explains me how we can implement a diode in CMOS technology.

One option is BC shorted BJT.

Any other options?
 

cmos back diode

How to make a parasitic BJT?
 

**broken link removed**

or razavi's Design of analog cmos integrated circuits

make help
 

hi,

actually you don't make a parasitic bjt. as the name implies it is parasitic. it is inherent from the cmos structure. if you have an nmos transistor, parasitic npn bjt would be, n for drain p for the substrate and another n for the drain.

to make a diode in cmos. connect the gate to the drain in either pmos or nmos. then you have a diode connected mos or a diode (as the name implies).

hope this helps.

- al :)
 

In standard p-sub CMOS process, you got two diodes.
One is N+/p-sub. You just draw a N+ region in layout. It form a diode between N+/p-sub. One thing to note: p-sub is always connected to ground.
Another one is NW/P+ diode. You can draw a NW first, then add a P+ inside NW region.
To accurate performance simulation, you must find help from your foundry.
 
On their respective substrate, for ndiode jz draw N+, contact, Metal1, Dum_dio. For pdiode draw P+,contact,Metal1,and Dum_dio.

Dum_dio or dummy_diode is a layer use by LVS to recognize that the device is a diode.

The size of the diode depends on the area of P+/N+ properly enclosed by Dum_dio.
 
Nowadays, Diode layer is also used. They are used with a tap to differentiate anode and cathode. Cathode is the one with the tap.

Regards,
ukint
 

ukint said:
Nowadays, Diode layer is also used. They are used with a tap to differentiate anode and cathode. Cathode is the one with the tap.

Regards,
ukint
Click to expand...

Attached is the Picture of what exactly you are saying about , this might be the implementation in Standard cell architecture, where in, the area of diode layer is proportional to the current capability of diode , but when it comes to Analog/IO design mostly the MOS implementation of diode is formed by shorting drain and gate as one terminal and source and bulk shorted together acts as another terminal (This always ensure device operates in saturation region)
 

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