Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Analog Design Question

Status
Not open for further replies.
master_picengineer

master_picengineer

Banned
Advanced Member level 3
Joined
Sep 3, 2007
Messages
848
Helped
66
Reputation
132
Reaction score
16
Trophy points
1,298
Activity points
0
Hi all,
I designed and simulated a flip-flop at transistor level and I wish determine set up and hold up times as well as the maximum clock frequency that can clock this flip-flop.
How can I do this ?
Any reply is welcommed.
Thanks in advance.
 

setup time:
1. set flip-flop to 0(1)
2. change data edge 0->1 (1->0) at T before clock edge
3. check flip-flop out
3.1 if D==1 (0) then T = T-dT
3.2 if D==0 (1) then T = T+dT
4. check accuracy of T, if not satisfactory go to 1


hold time:
1. set flip-flop to 0(1)
2. change data edge 1->0 (0->1) at T after clock edge
3. check flip-flop out
3.1 if D==1 (0) then T = T-dT
3.2 if D==0 (1) then T = T+dT
4. check accuracy of T, if not satisfactory go to 1

We use bisection division method for determine setup und hold time.
 
Hi Kola,

What is this bisection method? Can you please explain?
any materials regarding the same would be very helpful.

Thanx
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top