Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to understand DDR SDRAM cell bank

Status
Not open for further replies.
E

EDA_hg81

Advanced Member level 2
Advanced Member level 2
Joined
Nov 25, 2005
Messages
507
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Activity points
4,808
The follow picture shows the structure of DDR SDRAM cell array.

“8192” means 8192 rows.
“512” means 512 columns.
But what “36” means, why it is not “16”? Since data bus width is 16.

Thanks.
https://obrazki.elektroda.pl/69_1194554792.jpg
 

It looks like it means that there are 32 Bank0 memory arrays of 8K x 512. The picture implies there are many of these arrays
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
x32 (not 36 as you have mentioned in the question) does mean that it is a 32 bit data width SDRAM. Make sure you are referring to the diagram from the correct datasheet.
AA (Rows) x BB (Columns) xx DD (Data bus width)
Correction to the earlier reply: There are four banks (not 32) as per the diagram. Only recently we are getting SDRAM chips with 8 banks, 32 banks is still far away i guess.
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
36 means it is internal parity bit, also sometimes micron makes mistakes in there data sheets I can point few
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
when we refer to specific column in each bank, the data width is 16 or 32?

The I/O databus width of DDR SDRAM is x4, x8, x16. How I can use this 32 bit wide?

Sorry for my early mistake it should be '32'.
 

because it is DDR double data rate that's why we are referring 32 bits bus instead of 16
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Thank you.

I understood
 

I am still confused.

The following diagram shows the read burst (BL = 4).

BL = 4 means four columns location have been selected and every columns location inside cell array is 32 bit wide.

If we use double bumping way to output data on each column location, there should be 8 data outputs in series.

I am wondering how we can capture those 32 bit wide data when external data bus is only 16 bit wide.

Thanks.
 

Hi,

Can you provide the part number of the DDR SDRAM you are using? I might be able to understand your problem if I go through the full datasheet.

-Naren
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
Just to continue with my earlier reply, the DDR memroy chip will have internal data bus width which is twice that at the external bus. By this it manages the double data rate with 2n prefetch. It captures 16 bits on positive edge and 16 bits on negative edge. The entire 32 bits are then used internally in one clock cycle. This also explains why there is x32 instead of x16 in the datasheet.
The burst length (BL) you have mentioned is the number of words (in this case 16 bits) you can read (or write) continuously without issuing the command again.
I hope it is bit clear now.
 

    E

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
arnarendra

It is 512Mb DDR SDRAM made by Micron.

Thank you for your answer.

I confused the burst length with the column location early.

It is very clear if burst length equals to the number of the words

Thank you so much.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top