How to equalise net lenght??????

specctra sdram pcb

Hi Guys
I am new to PCB design. Can any one pls tell me how to equalise net lenght. I have a fpga and a Microcontroller on the pcb and need to route the address and data bus. the pcb is a 4 layer and i am trying to route data on top layer and add on bottom layer.
Due to pin layout of the buffer for add and data bus, nets having different lenghts....

thus can any one pls tell me how to equalise them. i read at many places that try to route them in a zigzag manner. At the same i also read that routing of data and address bus should be parallel, i mean all the add and data lines should be parallel to each other... this is contraditory to what is said in equalise net lenghts...

guys pls help me understand this more clearly...

thanks in advance
tama

equalise net length

Hi,

As far as possible try make the length for both data and address equal,if not less skew because of the density...

Check this links below,you might find solution for your query

https://www.ultracad.com/mentor/mentor signal timing1.pdf

https://www.ultracad.com/mentor/mentor signal timing2.pdf


Regards,

Ramesh

The fastest way to achieve equal net lengths Is to use an Autorouter such as specctra to do the routing. You will have to define rules setting up min and max trace lengths. I do this regularly when routing DDR Ram...

In PCB Tool:
1. Create a class (for this exersize lets name the class "length_match") for all signals that require length matching.
Class and rule setup differ between Layout platforms. So this will depend on what layout tool you are using.
2. Add all desired nets to class: length_match
3. Set the min and max net length for nets in class. (for DDR Ram it is usually +/-25mils for D's and other critical signals) One way to find this out is to route the longest connection first, then base all other signals on this one.
4. In this case since it is a 4 layer board I would also setup class to route only on layer 1 and 4 eliminating internal layers. Also, if possible I would NOT allow autorouter to place vias when routing. This can be defined in class rules of layout tool.
5. send database to router and autoroute only class "length_match".

It will take a few passes to do but at the end of the day you will have very equal lengths. much closer than trying to do it manually. Believe it or not it will also save T-I-M-E....

I will be happy to help you further if needed.
Eda

Hi Rame, edaedaeda

Thanks for your replies, and the information you gave.

edaedaeda, I am using altium desiner 6.7. can you pls give more info on how to set it up in alitum desiner 6.7. the pcb contains microcontroller, fpga, sdram and a expansion board connector. the main problem what i have is that not the entire address, data bus goes to all the devices. in this case how to match the nets. eg address bus is A[20..1] but now only A[11..0] goes to expansion board, A[16..1] goes to fpga(which is being used as a ram), A20..0] go to sdram.

as per the placement, SDRAM is very close to the microcontroller, then fpga and then the expansion board connector. and i am facing problems in matching these nets.

In altium desiner there is a option for equalise net lenths, and autorouter but it dosnt route properly. Have anyone used this before, if so pls help me in setting it up.

I am new to this software as well hence asking lots ????.

Thanks in advance.
Tama

Just follow the steps below.
1. Go to design rules.
2. Select High speed option.
3. Select matched net lengths, right click mouse and select new rule.
4. Select the net class and set the length.

Hi eswar_babu77

I tried the way you have suggested but when i start the auto route it routes in a very hap hazzard way... can you pls help in this... do i need to set anything else...

thanks in advance

tama

hi ,

how to set the length matching in cadence allegro 16.2??

you have to set the constraints in Constraint manager as per your need..

How can this be done in Mentor Expedition PCB ?

Manual and help files:smile:

Thanks ..