How to set the core_gen signal ?

Every time when it data latched
on positive edge of clock it must be at the centre

anyone know how to do it

core_gen

What is "it"?

core_gen

Is this what you need? Center of Data is always at positive edge of the clock.

initial begin
for(i=0; i<256; i=i+1) begin
data <= d'd0;
@(negedge clk);
end
$stop();
end

Re: core_gen

question is not clear.

core_gen

negative edge of clock send data,
positive edge of clock receive data (maybe worry)

BR.
ls000rhb

core_gen

if u are talking with reference to Memory and your design interface,then use inverted clock for Memory when your design is working at clock.

core_gen

Anyone please help me

i need to create a Core_gen
which send the signal through a ADC ( Analog-to-Digital converter )

Anyone know how to set the core_gen Signal !!
list me the step please~
thanks

Re: core_gen

send signal through ADC? or send signal to ADC? detail your requirement, others can help you.

Re: core_gen

i need a signal Generator go in to ADC and come out with 10 bit Digital
anyone know how to do it please~~

core_gen

Well Man!!!

Why u asling this question from FPGA men !!!!


ADC is very simple

IC's are available for that


and by the way FPGA works only on digital signals not analog ones !!!!!

YEs you can use an ADC chip before FPGA

and use ADC output to process for some information in it



and to build a simple signal generator use LUTs or Primitives etc in FPGA


or use Microcontroller for that

Even a DSP Processor would work


Do what u feel easy about

Re: core_gen

becos im noob to this VHDL

core_gen

yup i got the IC . just that i don know how to start on signal Generator .. ( if is a Core_gen i can still work on it ) but kind of different err anyone help

Re: core_gen

i need to link the output of the ADC to the DAC
meaning ADC output to DAC input ( 8bit to 8bit )
( anyone know how to write in VHDL )
anyhow please help ~~

Added after 5 hours 5 minutes:

i need to link the output of the ADC to the DAC
meaning ADC output to DAC input ( 8bit to 8bit )
( anyone know how to write in VHDL )
anyhow please help ~~

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity assign4 is
Port ( X : in STD_LOGIC_VECTOR (9 downto 0);
res : in std_logic;
m_clk : in std_logic;
out0, out1, out2, out3, out4, out5, out6, out7 : out STD_LOGIC_VECTOR (9 downto 0));
end assign4;

architecture Behavioral of assign4 is
type State_type is (S0,S1,S2,S3,S4,S5,S6,S7);
signal current_state,next_state : state_type;
Signal p0,p1,p2,p3,P4,P5,P6,P7 : STD_LOGIC_VECTOR(9 downto 0):="0000000000";

begin

process (m_clk, res)
begin

If res='1' then current_state <= S0;
elsif m_clk'event and m_clk='1' then

current_state <= next_state;
end if;
end process;

process ( current_state, X )
begin
case current_state is

when S0 => p0 <= X;
next_state <= S1;
when S1 => p1 <= X;
next_state <= S2;
when S2 => p2 <= X;
next_state <= S3;
when S3 => p3 <= X;
next_state <= S4;
when S3 => p4 <= X;
next_state <= S5;
when S3 => p5 <= X;
next_state <= S6;
when S3 => p6 <= X;
next_state <= S7;
when S3 => p7 <= X;
next_state <= S0;

end case;
end process;

process ( current_state )
begin

if current_state <= S0
then
out0 <= p0;
out1 <= p1;
out2 <= p2;
out3 <= p3;
out4 <= p4;
out4 <= p5;
out4 <= p6;
out4 <= p7;
end if;
end process;
end Behavioral;

Re: core_gen

jason here..wahaha...finally i graduate le....

u...better look after the newcomer worx...=D

Re: core_gen

WHAHA so nice done with the project . Mr Lai got say anything at the last day ( i was not there ) keke
take care my friend

Re: core_gen

hahas...u saw my project meh?? mr lai show u 1?? did he say anything about it??

actualli there are some flaws in the project...but i tried to cover it up..hahas..dun tell him worx....

mr lai didnt say anything on the last day...he juz say.."ok lahs...can...u can go now...good luck to ur attachment..=D"

Re: core_gen

wowow i was sick that day . so never got a chance to come and see.. keke soo good ^^ he still wish you good luck muahahaha . what are you doing so free now

Re: core_gen

jason
where are you
i need to ask you about DDS
help~~~
reply me asps
tmr afternoon i need to test hope you see this message
drop me email ( hey_56@hotmail.com )
how to make the DDS
8bit
120MHZ

10bit cannot test need 8bit

core_gen

if u are talking with reference to Memory and your design interface,then use inverted clock for Memory when your design is working at clock.

That is quite reasonable......

core_gen

is it related to core_gen?