Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

conversion difficulties (from VHDL to Verilog..!)

Status
Not open for further replies.

salma ali bakr

Advanced Member level 3
Advanced Member level 3
Joined
Jan 27, 2006
Messages
969
Helped
104
Reputation
206
Reaction score
21
Trophy points
1,298
Activity points
7,491
icarus verilog vhdl conversion

Hi,

I'm converting some codes from VHDL to Verilog, and I have some difficulties in:

for example in VHDL, we can write something like that:

d : in std_logic_vector; --unconstrained vector or ports

where the size of this vector is determined at instantiation by the width of the input signal connected to it...what's the similar form of this in Verilog, if any?

...

Also, if I'm using this vector in the architecture, I'll use signal'range since I don't know its width, what's the similar to it in Verilog, if any?
d <= (d'range => '0');

thank you :D
 

Hi

What tool you use?

tnx
 

modelsim...

are unconstrained ports (VHDL) supported by all tools...?
is there something like them in Verilog...???
 

In Verilog you can set some Parameters or Defines.
One to one conversion is difficult, especially when Verilog can probe signals inside modules..
 
AA Salma,
Try this free tool at http://www.ocean-logic.com/downloads.htm
In addition to this, any HDL compiler that compiles both languages can make conversion. Check your tool documentation.
BR,
Amr Ali.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top