didibabawu
Member level 5
1. H. Kohno and Y. Nakamura et al., “A 350-MS/s 3.3-V 8-bit CMOS D/A
converter using a delayed driving scheme,” in Proc. IEEE 1995 Custom
Integrated Circuits Conf. (CICC), May 1995, pp. 10.5.1–10.5.4.
2. A. Marques and J. Bastos et al., “A 12-bit accuracy 300 MS/s update
rate CMOS DAC,” in Proc. IEEE 1998 Int. Solid State Circuits Conf.
(ISSCC), Feb. 1998, pp. 216–217.
3. A. Van den Bosch and M. Borremans et al., “A 12-bit 200-MHz lowglitch
CMOS D/A converter,” in IEEE 1998 Custom Integrated Circuits
Conf. (CICC), May 1998, pp. 249–252.
Thank you very much.
converter using a delayed driving scheme,” in Proc. IEEE 1995 Custom
Integrated Circuits Conf. (CICC), May 1995, pp. 10.5.1–10.5.4.
2. A. Marques and J. Bastos et al., “A 12-bit accuracy 300 MS/s update
rate CMOS DAC,” in Proc. IEEE 1998 Int. Solid State Circuits Conf.
(ISSCC), Feb. 1998, pp. 216–217.
3. A. Van den Bosch and M. Borremans et al., “A 12-bit 200-MHz lowglitch
CMOS D/A converter,” in IEEE 1998 Custom Integrated Circuits
Conf. (CICC), May 1998, pp. 249–252.
Thank you very much.
