Problem with Altium Designer

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"Embedded Board Array" creates array of one board, I want to combine two different board.
After finishing board design, which other info or may be logos do I have to add to board? company logo, board version , . . .? which layer is recommended for each data?

Which special care we must take for bga device in board design? is via tenting just enough? do we need to inform the pcb fab about existing of bga devices on board?

Is via tenting a common practice in most multi layer boards?

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No... the embedded board array can combine as many different boards as you want on one panel. It is NOT just for one board design. The last embedded board array I did had six pieces each of three different designs on one panel. You just have to remember that ANY PANEL REQUIRES THAT ALL THE BOARDS HAVE THE SAME STACKUP AND LAYER NUMBERS. You can't panelize boards with different stackups or numbers of layers using any software tool.

Your company logo would normally go on the top overlay (silkscreen). Board version might go on either the top or bottom. There's no standard - it depends on the desires of your company, and how the board will be mounted. If the board is screwed down to a chassis, you won't be able to see things placed on the bottom copper or silkscreen layer - it makes sense to put that sort of information where it can be seen when the board is mounted.

Look at the vendor's application notes for The BGA you are using. They will have any recommended limitations for solder mask or tenting. Some BGA's might use mask delimited pads. Tenting of vias under the BGA is common.

The fab doesn't care whether a pattern on the board is BGA, TQFP, or ... Their process is the same regardless of what footprint you have placed. You tell them how to finish the board and what tolerances are allowable in the fab notes you provide with your Gerber files.

Via tenting is only used when needed to keep solder off, or out of vias. It depends on your assembly process (i.e. what kind of solder process you are going to use). It is common with wave soldering.

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in your merged desin, who was responsible for cutting the final boards? do you have your own cuttine machines or your vendor did this job for you? if the vendoe was responsible, how did you informed them about merged boards and cut shape and sizes? how much space did you preserved between boards?

situs autorouter

Usually you can just tell the board house to cut the boards.

By looking at the gerbers generated it is pretty easy to distinguish between the different boards and they will cut each board out for you if you ask. Check with your board house.

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Do this cutting require "CNC Cutting" or will be done by simple methodes like V-Cutt?

tps54610 orcad

They could either just route it, or v-score it in which case you can snap it off when you receive it.

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You tell the fab with design notes how you want the boards to be separated from the panel. Usually, you will place lines on a mechanical layer to define the outline for V-Scoring or routing. This can be done either in the files for the individual boards, or on a mechaincal layer in the Embedded Board Array or the panel you define in CAMTASTIC.

There are several ways to break boards out of a panel. If you don't plan to have assembly done at the panel level, you simply define route outlines so the fab can completely route the boards from the panel for you. If you plan to have assembly done at the panel level, you will need to define lines for V-Scoring, or you will have to show "mouse bites" on the panel for breakaway tabs.

The distance for separation of the boards should be discussed with your assembly house if the boards are going to be stuffed and soldered as a panel. Otherwise, you should discuss the issue with your fab to see what size tool they will use for routing out the board. You need to leave them enough room so they can route the outline or score without cutting into an adjacent board.

A lot of your questions could be answered by the fab. If you called them and perhaps took a tour, you could become more familiar with how boards are made and panelized.

problem with altium designer gerber files

what about DRC errors in board merging, by just copy and pate errors might arise!
is design finishing as a criteria for panelization? or we can edit it even after merging and panelization is as a place-holder?

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When using the embedded board array...it doesn't copy your board into your new design rather it just reads the original and places it on your board, so if you want to edit things on your array, you just go back to the individual boards and edit and save.

The best way is to use the embedded board array. You will not get any DRC errors unless the individual board already have DRC errors. Also as house_cat already said, they all have to have the same exact layer stack-up.

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- What does "Coupons" mean in PADS?
- what is the meaning of FCC logo? and do I have to place it on board?
- Also what does "Trash can icon with a cross on it" mean? is it related to ROHS?

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"Coupons" refers to test coupons which can be made by the PCB fab to verify the impedance characteristics of a circuit board. See the discussion at: https://www.polarinstruments.com/support/cits/AP124.html

The "FCC" marking means that your board meets the testing requirements of the
Federal Communications Commission for signal emissions. It is an EMC marking.

The trashcan with an "X" through it means that the board is not to be disposed of by placing it in a regular trashcan. In many places in the world, a populated PCB must be handled as hazardous waste. It can only be disposed of through an approved recycling center.

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1) Line impedance is related to dielectric material, dielectric thickness, conductor width and thickness, and stackup. In pcb design and fab notes we specify almost all of these features, but in fab notes again we have one or more sentence that inform fab about existence of impedance controlled line! When we had determined each parameter, why we need to inform fab about those lines? Some fab notes ask fab to do the impedance controlling! I am wondering how fab can control the impedance!

2) What does ARTMASTER mean in fab notes?

3) We always put a layer number on related layer. Other than bottom layer, which layer code must be mirrored? Is there any specific rule for layer codes?

4) Net-Name showing on PCB tacks and pad is very useful for placement and manual routing! Is PADS able to show the net-name, as AD? What about Allegro

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1. Only the fab knows the exact dielectric constant for the batch of material they will use to make your board. You tell the fab what impedance you are targeting, and they make use of the data included with the dielectric to make small adjustments in the trace width to achieve the desired impedance. Many fabs, especially the better ones, have Polar field solvers they use to calculate layer-by-layer impedance for the desired stackup. That's what they use to adjust your traces. The better fabs also provide TDR verification of impedance for the finished board, so you know that you got what you asked for.

2. Artmaster probably refers to a Gerber drawing. Where did you see it?

3. Layer numbering in copper is normally only done for coupons to verify stackup. There is no standard. If you use layer numbers, you want them to be visble when holding the board up to light so you can verify the stackup order yourself. Plane layers are negative layers, so a window needs to be provided in the copper for plane layers. Since you are viewing the numbers by looking through the board from one side, the bottom number is the only one that needs to be reversed - it will appear backwards when you look at the bottom of the board, but normal if you look through the board.

4. No, PADS and Allegro do not display the net name the same way as Altium Designer. You can get a status line display of the netname, but you don't see the netname in text on the objects in the layout window.

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1)I saw the ARTMASTER in Xilinx Boards, it was
“USE ARTMASTER # ML405” in fab notes.

2)On this board they have layer stackup legend in similar way as AD! It is interesting for me to know how to generate and add to PCB file in PADS or Allegro. Also they have Drill legend on other reference design!

3)Is vendor same as fab, or it refer to some one else?

4)Regarding impedance control, I was supposed that we are specifying the material in fab note! Also do you mean that they may change the mask data and track width to reach to targeted impedance, or tune it?

5)In pick and place process, both the designer(in PCB data) and P&R machine exactly know the placement data, I am wondering what is the use of FID in this situation? What information it carry? Is it accurate enough to be used as guide of placement?

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Memory does a lot help on speed.

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Johnson said:

- what is the meaning of FCC logo? and do I have to place it on board?

Click to expand...

You do not have to place the FCC logo on the PCB. For FCC part 15b, you have to have the logo marked somewhere on the label. For transmitters the FCC ID # needs to be marked on a label somwhere. The label needs to be placed on the exterior, or in a battery compartment like cell phones.

- Also what does "Trash can icon with a cross on it" mean? is it related to ROHS?[/quote]

The trash can is related to RoHS, its part of the WEEE directive. More information here and in the attached pdf.

https://ec.europa.eu/environment/waste/weee/index_en.htm

altium blind vias problem

I would like to repeat my last questions again! thank you.

adding notes to altium designer 6

1. The Artmaster note is obviously something internal to Xilinx. I don't know what they are refering to. It certainly isn't anytihng standard in the industry.

2. In PADS or Allegro you have to draw the stackup legend - it isn't automatically generated.

3. When they refer to vendor, they usually mean the fab.

4. It is customary to let a trusted fab tune the traces to meet the impedance goal. They are the only ones who have the exact numbers for the dielectric constant of the material they will use for your particular board. The dielectric constant varies from one batch of the same material to another. The dielectric manufacturer includes the test data with each batch of materials he sells.

5. FIDs are used to allow the assembly house to set up their machines using optical targeting. The FID acts as a reference point to ensure that the machine is accurately aligned to the board. Not only are FIDs used to align to the board, but high pin count IC's should also have their own FID at two corners to allow alignment for placement. There's a good discussion at: https://www.tkb-4u.com/articles/other/fiducial/fiducial.php

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"The trashcan with an "X" through it means that the board is not to be disposed of by placing it in a regular trashcan. In many places in the world, a populated PCB must be handled as hazardous waste. It can only be disposed of through an approved recycling center. "

IT SEEMES THAT OUR JOB IS HAREFULL!, AND WE SHOULD TAKE CARE OF OURESELF

altium drawing problems

Which soldering method could be used for SMD devices?