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How to distribute the hi-voltage and negative voltage in flash memory design?

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sastromuni

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i need help with flash memory design

currently, im stuck on how to distribute the hi-voltage and negative voltage generated from charge pumps to the wordlines and not making the transistors breakdown.

anyone have any ideas how to do this?

thanks
 

Re: Flash memory design

Hi
I think we donot have negative voltage in FLASH.
We have a reference voltage then negative voltage means lower that this reference.(suppose ref-=-1 in ref=1.5 it become ref-=0.5)
if i want to explain it for you in another form,ref is virtual ground.

BYE
 

Flash memory design

we use level shifter circuit to boost gate control and tripple well N-device to pass negative voltage in flash memory.
 

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    sastromuni

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Flash memory design

hi
is it a must to use triple well process to pass negative voltage? can we just use pmos device to pass negative voltage?
i know that pmos device is not good at passing negative voltage, but what is the consequence of using it? for example if i use 0.18 um process and try to pass -12V using pmos, what is the passed output voltage?

thanks:)
 

Flash memory design

for flash memory designer,
it would be great if you could share you exp in designing flash memory circuitry(decoder,driver,etc)
and also what process are you using (standard CMOS or HVCMOS?)
 

Re: Flash memory design

I am not very familiar with the Flash Memory design, however the fllowing two tips may help you
One is the MOS breakdown voltage is refer to the voltage difference between two terminals of the transistor, so just to make sure the voltage difference of any two terminals not exceed the maximum breakdown voltage.
Another is using round shape gate design can improve the gate breakdown voltage.

hope these help.
 

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    sastromuni

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