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The reason tht "hold time " is more imp cos, in case of the hold chk, the timing is done at the current edge of the clk, i.e the capture of previous data !!
but incase of setup, the capture is done after one clk cycle . so evn if ther is a setup viol after silicon hz come bk u can reduce the freq of the design and still wrk with it !!
fixing hold violation is more imp than fixing setup !!!
i assume that u connect a crystal external to the chip .... so if ur chip doesn'nt wrk at say 40Mhz, then reduce the frequency by using a lesser value crystal ... say 20Mhz .....
this method can be used if u use a crystal connected externally .. this avoids "re-spin" of the chip !!!
case2: if u r usin a "clk osc" IP blk
In this case, u have to replace the existing IP by a another one which is of lesser freq.
This case requires a "re-spin" of ur design & does'nt cost u so much if u wer to go for a complete re-spin of ur chip !!!
setup time is the time when we place our data on the adderess bus or data bus.this is due to the transitions(Surges).so it should be greater than hold time.
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