kun
Member level 2
for now i still a newbi to the whole Xilinex and modelsim
all i know is that i need to write a codes in the Xilinex create a VHDL module
and follow by VHDL Test Bench
using the Test Bench codes and run Modelsim
i should be able to get a wave
i try for 2 week but still i cant see a wave
>> ( simple coding for try out ) and it also not working ( up counter ) <<
no compile Error
all i can see just green line
can anyone let me know is there any setting
<< VHDL Module >>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture rtl of counter is
signal Q: std_logic_vector (3 downto 0);
begin
process ( clk,rst)
begin
if rst='1' then
Q<="0000";
elsif (clk='1' and clk'event) then
Q<=Q+"0001";
end if;
end process;
count<=Q;
end rtl;
<< Test Bench >>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testcnt_vhd IS
END testcnt_vhd;
ARCHITECTURE test OF testcnt_vhd IS
signal clk,rst : std_logic;
signal count: std_logic_vector (3 downto 0);
constant clk_period : time:=100 ns;
component counter
port (clk,rst: in std_logic;
count: out std_logic_vector (3 downto 0));
end component;
begin
U1: counter port map(clk,rst,count);
process
begin
clk<='1';
loop
wait for (clk_period/2);
clk<=not (clk);
end loop;
end process;
-- reset counter
process
begin
rst<='1';
wait for 320 ns;
rst<='0';
wait;
end process;
end test;
all i know is that i need to write a codes in the Xilinex create a VHDL module
and follow by VHDL Test Bench
using the Test Bench codes and run Modelsim
i should be able to get a wave
i try for 2 week but still i cant see a wave
>> ( simple coding for try out ) and it also not working ( up counter ) <<
no compile Error
all i can see just green line
can anyone let me know is there any setting
<< VHDL Module >>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture rtl of counter is
signal Q: std_logic_vector (3 downto 0);
begin
process ( clk,rst)
begin
if rst='1' then
Q<="0000";
elsif (clk='1' and clk'event) then
Q<=Q+"0001";
end if;
end process;
count<=Q;
end rtl;
<< Test Bench >>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY testcnt_vhd IS
END testcnt_vhd;
ARCHITECTURE test OF testcnt_vhd IS
signal clk,rst : std_logic;
signal count: std_logic_vector (3 downto 0);
constant clk_period : time:=100 ns;
component counter
port (clk,rst: in std_logic;
count: out std_logic_vector (3 downto 0));
end component;
begin
U1: counter port map(clk,rst,count);
process
begin
clk<='1';
loop
wait for (clk_period/2);
clk<=not (clk);
end loop;
end process;
-- reset counter
process
begin
rst<='1';
wait for 320 ns;
rst<='0';
wait;
end process;
end test;