EDA_hg81
Advanced Member level 2
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xst directed routing
I am wondering the Directed routing constraints as follow is generated by RLOC , etc constraints or it is generated by FPGA editor?
Should I include all them in my code for utilization?
Thanks for all idea.
I am wondering the Directed routing constraints as follow is generated by RLOC , etc constraints or it is generated by FPGA editor?
Should I include all them in my code for utilization?
Code:
constant drtFOO_K1_RIGHT : string :=
"{2;1;-7!-1;56800;42552;14;90;132;35;13!0;" &
"-232;-1323;25!1;-4416;784;2!2;984;1048;0!2;-3415;51!2;3463;-323!3;160;" &
"-93;4;87;133;12!4;-3296;416;4;84;134;19!5;3296;-688;4;87;132!}";
Thanks for all idea.