vikasvij1982
Newbie level 5
![Newbie level 5](/styles/images/ranks/blevel2.gif)
Hi everybody,
I am stuck in a very odd spot in my tool flow. I am working on some asynchronous modules which is working with synthesized synchronous module. i am able to generate the sdf file using Design Compiler, but i am not able to back annotate this sdf for testing in Modelsim. I have tried it with NC-Verilog, but its also not using the sdf file, instead for both i am getting the unit delay model based simulation results.
I wanted to ask you whether the version of sdf file and the support for that sdf file version in the tools can be an issue as i am using Design compiler version 2006.12 and my Modelsim version is 5.7c.
If anybody wants to share the steps which he/she follows for backannotation with some commands then that will also be a great help.
Regards
Vikas
I am stuck in a very odd spot in my tool flow. I am working on some asynchronous modules which is working with synthesized synchronous module. i am able to generate the sdf file using Design Compiler, but i am not able to back annotate this sdf for testing in Modelsim. I have tried it with NC-Verilog, but its also not using the sdf file, instead for both i am getting the unit delay model based simulation results.
I wanted to ask you whether the version of sdf file and the support for that sdf file version in the tools can be an issue as i am using Design compiler version 2006.12 and my Modelsim version is 5.7c.
If anybody wants to share the steps which he/she follows for backannotation with some commands then that will also be a great help.
Regards
Vikas