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vhdl code for MUX(1-16)

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vhdl code for mux

What is your spec? How do wanna realize the MUX?
 

vhdl code mux

Hi this is a 8x1 mux... you can make 16x1 from it...

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
END ENTITY mux;

--
ARCHITECTURE mux OF mux IS
BEGIN
process(s,inp)
begin
case s is
when "000"=>op<=inp(0);
when "001"=>op<=inp(1);
when "010"=>op<=inp(2);
when "011"=>op<=inp(3);
when "100"=>op<=inp(4);
when "101"=>op<=inp(5);
when "110"=>op<=inp(6);
when others=>op<=inp(7);
end case;
end process;
END ARCHITECTURE mux;
 

vhdl code for 4 1 mux

hi,

you will get the idea for ur code from any VHDL book. As it is a basic unit digital system. Every book atleast has this
 

4 1 mux vhdl

lordsathish said:
Hi this is a 8x1 mux... you can make 16x1 from it...

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY mux IS
port(s:in std_logic_vector(2 downto 0);
inp:in std_logic_vector(7 downto 0);
op: out std_logic);
END ENTITY mux;

--
ARCHITECTURE mux OF mux IS
BEGIN
process(s,inp)
begin
case s is
when "000"=>op<=inp(0);
when "001"=>op<=inp(1);
when "010"=>op<=inp(2);
when "011"=>op<=inp(3);
when "100"=>op<=inp(4);
when "101"=>op<=inp(5);
when "110"=>op<=inp(6);
when others=>op<=inp(7);
end case;
end process;
END ARCHITECTURE mux;
Click to expand...

I think there is no need to use ieee.std_logic_arith.all library.
Besides you can also use GENERATE statement instead of case.
or use INTEGER as input so no need of case or generate statement.
 
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