Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What's effect on max_fanout and max capacitance violation?

Status
Not open for further replies.
V

vidarson_qin

Newbie level 3
Newbie level 3
Joined
Aug 31, 2007
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,307
max capacitance

What's effect on max_fanout and max capacitance violation?
Currently,my design has no timing violation and max transition violation,but there are still 2 violations:max fanout and max capacitance violations on the system main clock, which I have set "dont_touch_network" properties on this clock path.

Must I fix these 2 violations?And how can I do that?
I need ur help,thanks in advance.

Best Regards,
Vidar
 

max_fanout

Depends on which step in the flow. If you are working on logic synthesis, you dont need to fix on clock netowrk. Physical design tools works bettwer to build clock tree and optimizes for DRC violations too..
Hopefully your CTS will fix DRC on the clock lines..

Regards,
Sam
 

max_fanout max_capacitance difference

set_ideal_net & set dont_touch_network together.

Generally, clock and reset are high fanout net which should be handled by backend tool.

David
 
max capacitance violations

hi,Sam:
Yes, I'm working on logic synthesis. So the physical design tools will fix the violations for me.
hi,David:
I have a try with both set_ideal_net & set dont_touch_network. It works! There is no violations! But I still compared the netlist with the previous one.I found there is nearly no difference between them. So is it to say that "set_ideal_net" on clock pin can only suppress the warnings:max_fanout and max_capacitance on the clock pin?
 

fix capacitance fanout violation

hi ,vidarson_qin:
the max fanout is the number of cells (for example AND2)drived by output signals, here is the clock signal.
but the max cap equals to cap per cell * fanouts
so what's the problem? I think you can fix it quickly!
Regards,
Arthur
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top