Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

RTL optimization tips

Status
Not open for further replies.

elec_student

Member level 1
Member level 1
Joined
Nov 21, 2005
Messages
41
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,288
Activity points
1,564
Hi,
I am facing some slack problem while synthesis of my RTL. I tried optimizing but not to much effect. Can anyone tell from where I can get some insight of various optimization techniques for improving delay in combinational blocks.

Thanks
elec
 

break ur larger combo blocks by introducing pipelines.
Note that this will increase ur output latency.
 
1. Look for if-elsif-elsif type statements : they are a recipe for un-necessary delays
2. Look for nested if(s) : again recipe of un-necessary delays:
In both the above cases you must ensure that these constructs are not intentional to implement a priority scheme, then replace them by case statements
3. Look for state registers: code them one-hot
4. Look for for-exit loops: again they introduce un-intentional priority schemes
5. Try to move logic before/after registers in the critical path.
6. And of course as suggested, pipelining can be introduced, if nothing works.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com
 
I had problem with my 14bit adder as well.

Can you guys help? Thanks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top