Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
A.. Anand Srinivasan is right. The more output transistors (we call it fan out devices), the more capacitance. I am not too sure about Analog IC, but in digital IC it is often a better practice to limit the number of fan out devices to be less than 4 whenever possible.
For MOS transistor fanout of 50 is possible....It all depends on total load capacitance offered.....more the fanout slower the device....
But How power sourcing capability will affect Fanout in MOS?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.