an error about check_deisgn command in synthesis process.

the error infor is like below, please instruct me, thanks!

Warning: Parameter mismatch in linking reference 'non_recursive' by name.
Can't find design. (LINK-18)
Information: Building the design 'non_recursive' instantiated from design 'comb_0' with
the parameters "1". (HDL-193)
Warning: Can't find the design 'non_recursive'
in the library 'WORK'. (LBR-1)
Error: 'non_recursive' was not identified as a synthetic library module
and could not be successfully elaborated from design library 'WORK'. (LINK-10)


In design, i instantiate the module "non_recursive" four times like below.

non_recursive #(1) nr1(
.clk (clk),
.en (en_div2),
.rst_ (rst_),
.din (pdm),
.dout (nr1do)
);

non_recursive #(5) nr2(
.clk (clk),
.en (en_div2_2),
.rst_ (rst_),
.din (nr1do),
.dout (nr2do)
);

non_recursive #(9) nr3(
.clk (clk),
.en (en_div2_2_2),
.rst_ (rst_),
.din (nr2do),
.dout (nr3do)
);

non_recursive #(13) nr4(
.clk (clk),
.en (en_div2_2_2_2),
.rst_ (rst_),
.din (nr3do),
.dout (nr4do)
);

Is the problem related with the coding style or ...?

David

Re: an error about check_deisgn command in synthesis process

cut+paste code for module non_recursive as well

Re: an error about check_deisgn command in synthesis process

Maybe you didn't read/analyze the code for non_recursive block?

Ajeetha, CVC
www.noveldv.com

hi, quan228228

Maybe to set this variable "hdlin_auto_save_templates"

Sincerely,
Jarod

check whether u have given the command before compile option wherin u get the report of only the analyzed part..
if its after compile it has to be resolved.

Re: an error about check_deisgn command in synthesis process

jarodz said:

hi, quan228228

Maybe to set this variable "hdlin_auto_save_templates"

Sincerely,
Jarod

Click to expand...

Thanks. you are right. I set this variable before reading/analying this module, the synthesis is done.

David