Verilog HDL: Blocking and non-blocking statement

Hello,

Do you guys have any idea when to use
Blocking and non-blocking statement in Verilog HDL?

Thanks.

Hi,

blocking (=) is truly sequential statement.
It is executed by the simulator before the simulator moves forward to the next statement.

We only use it to design for pure combo circuit.

ex: assign out = a & b;
or
always @(a or b)
begin
out = a & b;
end

IMPORTANT: blocking is ORDER dependent.

non-blocking (<=) is scheduled and executed together with other non-blocking.

It is NOT DEPENDENT on the ORDER in which as assignment occurs.

OK, where to use it??
Use it when in clock association.

Hope it helps.

In general, Blocking can be used in combinational logic, and Non-blocking can be used in sequential logic.

use blocking for combinational and non-blocking for sequential.....

blocking is step by step process and it is the systhesis the comdination ckt
non blocking is the concurrent process and it is the systhesis the sequential ckt

vamsi

Blocking Statements: A blocking statement must be executed before the execution of the statements that follow it in a sequential block.

Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other. It means that nonblocking statements resemble actual hardware more than blocking assignments.

1 module block_nonblock();
2 reg a, b, c, d , e, f ;
3
4 // Blocking assignments
5 initial begin
6 a = #10 1'b1;// The simulator assigns 1 to a at time 10
7 b = #20 1'b0;// The simulator assigns 0 to b at time 30
8 c = #40 1'b1;// The simulator assigns 1 to c at time 70
9 end
10
11 // Nonblocking assignments
12 initial begin
13 d <= #10 1'b1;// The simulator assigns 1 to d at time 10
14 e <= #20 1'b0;// The simulator assigns 0 to e at time 20
15 f <= #40 1'b1;// The simulator assigns 1 to f at time 40
16 end
17
18 endmodule

When you guys said:
use blocking for combinational and non-blocking for sequential.....

what do it really mean? Cause in Verilog HDL, we are implementing the combinational logic within the block ( which is control by posedge CLK or nedege CLK).

For example,

always(@posedge CLK) begin
a = b+c;
d = e+f;
x = a&d;
end

In this example the statement within the block is combinational logic. And this combonation logic is located within the 2 flop control by the posedge CLK.

Can you help to explain in more details on this statement (use blocking for combinational and non-blocking for sequential)?

I will really appreciate your help. Thanks.

Hi cafukarfoo,

Your example is a combinational with a flip flop at the output.
Actually, your example is a sequential design.

Why?
Because you use clock edge.

When to use blocking (=)?
We use blocking when we want to design PURELY combinational circuit.
Example:

wire [2:0] x;
assign x = a + b;

OR

reg [2:0] x;
always @(a or b) // here I'm not using any clock edge (flops)
begin
x = a + b; // adder circuit (purely combinational)
end

As for non-blocking (<=), we use it for sequential circuit, where the circuit is using clock edge. Flop is a sequential circuit.
Example:

reg [2:0] x;
always @(posedge clock)
begin
x <= a + b; // there will be flip flops at output X
end

For better understanding, try to synthesis all the example given.
Before that my personal opinion, you need to understand both pure combinational circuit and sequential circuit.

Hope it helps.

Thanks no_mad for your help.

Refer to the link below. U'll get a good idea when to use blocking and when to use non blocking statements.

https://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf

Hi cafukarfoo,

in this post you will find info regarding blocking and non-blocking assignments

A blocking statement blocks the statements after it. A set of blocking statements execute sequentially.
A non-blocking statement does block the statements with it. they execute concurrently..

clliford's paper is best about verilog blocking and nonblocking assign statement. u can download it from sunburst-design