Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

load regulation of LDO

Status
Not open for further replies.
R

rock_zhu

Member level 1
Member level 1
Joined
Aug 18, 2005
Messages
40
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
Hangzhou,China
Activity points
1,526
load regulation

Hi all
I designed a LDO with 100mA max drive current and 1.2V output.I add a buffer between error amp and PMOS transistor.But when i do load regulation simulation the regulator output voltage is 1.3V at 1uA load current and 1.2V at 50uA or larger load current.
so why the curve like this? Does PMOS size too large or loop gain decreasing?
How can i get a stable 1.2V output voltage over the 0->100mA load current range.
Thanks advanced.
 

ldo load regulation

That drop is due to dc load regulation.To provide the high current value(more than your quiscent current), there will be certain drop across your PMOS o/p device..Usually dc load regulation will be a spec for your LDO.
 

    R

    rock_zhu

    Points: 2
    Helpful Answer Positive Rating
load regulation of ldo

rampat said:
That drop is due to dc load regulation.To provide the high current value(more than your quiscent current), there will be certain drop across your PMOS o/p device..Usually dc load regulation will be a spec for your LDO.
Click to expand...

thanks.
yes,this method is work by double the that branch's stastic current (10uA->20uA)but the whole current dissipation is limited, any other method?
 

load regulation for ldo

hello

try to increase overall loop gain to achieve better load regulation

regards
 

    R

    rock_zhu

    Points: 2
    Helpful Answer Positive Rating
ldo regulation

jutek said:
hello

try to increase overall loop gain to achieve better load regulation

regards
Click to expand...

Thanks. but if i increase the loop gain it is difficult to compensate although i add a buffer between error amp and PMOS. I find that the unit gain OTA buffer is diffcult to design in cmos standard process because the comon input voltage limitation.
 

nmos ldo operation point

What type of buffer you are using in the LDO?Is it a source follower (PMOS/NMOS) with unity gain or is it a gain stage (common source)?
 

ldo nmos operation point

dhasmana said:
What type of buffer you are using in the LDO?Is it a source follower (PMOS/NMOS) with unity gain or is it a gain stage (common source)?
Click to expand...


It is a unit-gain configuration NMOS input differential OTA. The input NMOS's Vth is high due to body effection. so the common input voltage is limited so as output voltage of buffer.
 

ldo source follower

Take a look on the operation point difference under different load condition.
If it has no problem, maybe you have to increase your loop gain such as using a bigger pass element.
 

load regulation in ldo

loop gain and transconductor of pass element will both influence the load regulation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top