jerry2007
Newbie level 5
![Newbie level 5](/styles/images/ranks/blevel2.gif)
hold time violation fix
I know clock should run reversely to avoid hold time problems for shift registers. But where/how should it be done in a standard design flow (We are using Cadence tools here)? My best guess is in the sdc file but I have no idea how to tell the tool about it... Thanks!
I know clock should run reversely to avoid hold time problems for shift registers. But where/how should it be done in a standard design flow (We are using Cadence tools here)? My best guess is in the sdc file but I have no idea how to tell the tool about it... Thanks!