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Help needed for the LUT based time delay code

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EDA_hg81

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The following is the code:

I do not understand how they set INIT for each LUT.

Code:
entity dqs_delay is 
             port (
		    clk_in   : in std_logic;
		    sel_in   : in std_logic_vector(4 downto 0);
		    clk_out  : out std_logic
		  );
end dqs_delay;

architecture arc_dqs_delay of dqs_delay is

component LUT4
   generic(
      INIT         :  bit_vector(15 downto 0) := x"0000" );
   port(
      O             :	out   STD_ULOGIC;
      I0            :	in    STD_ULOGIC;
      I1            :	in    STD_ULOGIC;
      I2            :	in    STD_ULOGIC;
      I3            :	in    STD_ULOGIC
      );
end component;		  
    
signal delay1     : std_logic;
signal delay2     : std_logic;
signal delay3     : std_logic;
signal delay4     : std_logic;
signal delay5     : std_logic;
signal high       : std_logic;


begin

high <= '1';   
   
one :  LUT4  generic map (INIT => x"f3c0")  
port map   ( I0 => high, 
             I1 => sel_in(4), 
             I2 => delay5, 
             I3 => clk_in, 
             O  => clk_out
            );
  
   
two :  LUT4  generic map (INIT => x"ee22")   
port map   ( 
            I0 => clk_in, 
            I1 => sel_in(2), 
            I2 => high, 
            I3 => delay3, 
            O  => delay4
           );
   
three :  LUT4  generic map (INIT => x"e2e2")    
port map     ( 
              I0 => clk_in, 
              I1 => sel_in(0), 
              I2 => delay1, 
              I3 => high, 
              O  => delay2 
             );
   
four :  LUT4  generic map (INIT => x"ff00")    
port map    ( 
             I0 => high, 
             I1 => high, 
             I2 => high, 
             I3 => clk_in, 
             O  => delay1 
            );
   
five :  LUT4  generic map (INIT => x"f3c0")    
port map    ( 
             I0 => high, 
             I1 => sel_in(3), 
             I2 => delay4, 
             I3 => clk_in, 
             O  => delay5 
            );
   
six :  LUT4  generic map (INIT => x"e2e2")    
port map  ( 
            I0 => clk_in, 
            I1 => sel_in(1), 
            I2 => delay2, 
            I3 => high, 
            O  => delay3 
           );

Any idea is appreciate.
 

The LUT4 is a 16x1 ROM. The INIT value simply initializes the ROM. See "LUT4" in your ISE Libraries Guide.

The code resembles post-route simulation code, an HDL representation of the routed FPGA, showing all the low-level details. It's intended for simulation, not for easy human understanding.
 

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
There are 16 possible states for the function with 4 inputs. Think about LUT (Look-Up-Table) as a simple bit vector with 16 bits defined(memory) and all inputs forms an address inside this vector. The INIT part inside every instantiation of the LUT4 component defines exactly this function with bits addresed by I(x) vector. This method of VHDL definition is used for direct placing logic inside FPGA resources and to avoid an additional optimizations which the synthesis tools can do.
Described method of signal delay is not good engineering practics but somtimes it helps solve some problems (but it may be terrible source of mistakes in the future or in another example of the FPGA)

bis
 

    EDA_hg81

    Points: 2
    Helpful Answer Positive Rating
go4sandesh_vsn

in my mind, it is intended for delaying CLK for few ns.
 

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