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How about the match of the PNP in cmos process

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bluesmaster

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I want to use the PNP in standard cmos process as levelshift. How about the match?
will it get the same match as the vertical pnp in bicmos process?
I not sure wether the match is relative to the Gm. In bicmos , the gm of pnp is
very high. So the offset is small. But in standard process, it is very small.
Anybody can evaluate the match of the bulk BJT, and the influence in the Bandgap design caused by the mismatch.
 

As you know, most bandgap in cmos process is implemented with lateral PNP. The match is good if you get a good layout even the beta is pretty blow about 15~30
 

waxtomato said:
As you know, most bandgap in cmos process is implemented with lateral PNP. The match is good if you get a good layout even the beta is pretty blow about 15~30
Click to expand...
I think the vertical PNP is used widely,do you think so?
 

You should use matching parameters of that factory on which be going to do the project. As a rule they are described in process specification. The majority of foundries offers bulk PNP with predefined layout. It is necessary to pay attention, that matching parameters vary depending on an Ie and Ic. If you parametres only as an estimation interest, it is possible to use the following:

sigma(dVbe)=0.1mV sigma(dIc/Ic)=0.25% sigma(dIb/Ib)=0.5%
 
bluesmaster said:
I want to use the PNP in standard cmos process as levelshift. How about the match?
will it get the same match as the vertical pnp in bicmos process?
I not sure wether the match is relative to the Gm. In bicmos , the gm of pnp is
very high. So the offset is small. But in standard process, it is very small.
Anybody can evaluate the match of the bulk BJT, and the influence in the Bandgap design caused by the mismatch.
Click to expand...

Gm is only dependent on Ic and Vt. So it has nothing to do with process. but beta is different.
 

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