salma ali bakr
Advanced Member level 3
I'm getting a bit confused these days about the word "layout"
is it the making of the mask layers for the IC ?
or is it the process of floorplanning and place & route ?
or are they at the end allll extensions to each other???
in an ASIC, when exactly do I do the mask layout for each transistor?
when it's a small design, or it's always done this way....???
should i see the P&R plan then do according to it the mask layout or what?
I'm confused about terminology and hierarchy of steps
thanks,
Salma
is it the making of the mask layers for the IC ?
or is it the process of floorplanning and place & route ?
or are they at the end allll extensions to each other???
in an ASIC, when exactly do I do the mask layout for each transistor?
when it's a small design, or it's always done this way....???
should i see the P&R plan then do according to it the mask layout or what?
I'm confused about terminology and hierarchy of steps
thanks,
Salma