What is body-biasing and how does it reduce power?

wat exactly body biasing is?? how this technology reduces the power?? thats static & dynamic power consumption??

can any one elaborate this?/

thanks in advance

body-biasing

Body biasing is a technique where the substrate/wells on the die are biased to something else then GND (in case of nmos) or Vdd (in case of pmos). This technique works well to reduce channel subthreshold leakage, does not do much for gate leakage and actually exacerbates junction leakage. It has little effect on dynamic power (the body biasing changes the source and drain junction capacitances to lower values, so it is not entirely useless).

Body biasing was very effective in processes down to 65nm as channel leakage was the highest static power contributor, in processes <65nm gate leakage is becoming on par or dominant so it is not as much use. Also, for <40 degrees C operation channel leakage is fairly low and gate+junction leakage dominate, so for idle load scenarios back biasing is not as effective as people expect even in higher geometries.