Minimizing process variation

How to minimize the process variation in my layout design? Any tips or idea?

Read best book

'The Art Of Analog Layout" by HASTINGS

we have three types of defects:-
1. Random defects - related to particle defects. mainly cause shorts and open.
2. Systemetic defects - induced due to process or lithography applications.
3. Parametric defects - when all the devices are working fine, but the specs like timing or power are not met.


for dimensions larger than 180nm, only random defects were important, but for dimensions less than 180nm all these have their contribution.


in your case you have to consider on the second point i.e. systemetic defects.



systemetic defects:-
Induced by process or lithography applications.
E.g. 1) Planarity.
2) Antenna effects.
3) Via opens (due to voids).
4) Electro migration.
5) RET issues – requires pitches.
- specific interactions on shapes between layers


foundaries provide some guideline rules to combat these systemetic errors.
these rules provide layout engineers with some layout styles, which when followed will reduce the percentage of systemetic defects........and hence improves yield.
E.g.
1) Poly end cap rules.
2) non minimum metal width and metal spacing.
3) Redundant vias, etc


these are included in the DFM rule deck, so you can check in the DRM provided by the foundary.........that will be the best place where you can find all these layout styles.


hope this helps you...........

stuck_adc made a very short but extremely usefull to newcomers to layout presentation for the process defects.

The various techniques for minimizing each of them are discussed in recomendations for each technology.
In general, I can add, that all techniques for minimizing mismatch or dc offset or other are valid for our discussion.

Think the physic behind all this:

If you have a 30 finger FET that will generate a BIAS current, then just laying out 30 fingures in a row will result to a degradation of the Ib you want to meet.
But if you split it to 15 fingures across 15 fingures you minimize the space on the waffer therefore the decradation across the space they occupy.
If you have two FETs, then interdigitizing them you get equal errors to both FETs ( you split them in equal parts and each finger of FET1 has the same degradation effect as each fingure of FET2) so at the output you will have a negation on the degradation.

Just follow simple physic and geometric rules and you will understand what you have to do ...

D.

stuck_adc said:

for dimensions larger than 180nm, only random defects were important, but for dimensions less than 180nm all these have their contribution.

Click to expand...

How about 018nm?

i am attaching a image showing the traditional defect limited yield and the feature limited yield..............here you can see that till 180um we get acceptable yield levels for all kind of defects.

NOTE - traditional defect limited yield only accounts random defects.
while feature limited yield accounts for systemetic and parametric defects.

the second picture shows - till 180um the feature size was comparable to the wavelength which we used for lithography process, but for features below 180um
we have feature size less than the wavelength. so we need special techniques like - 1) RET
2) RDR
3) DFM, etc.

you can confirm the 2nd and 3rd image for 130nm with different wavelengths used.