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Why Hold time does not depend on frequency?

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spartanthewarrior

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Hi All,

Can any body tell me why Hold time does not depends on frequency.

How can we remove it from the design.

Please provide me any document.
 

Hold Time

Because the launch edge and the capture edge is the same edge, the hold timing check doesn't depend on the clock period. You can add some delay cell on the data path to remove this timing violations.
You can refer to synopsys online documents.
 

Re: Hold Time

hold time : The time a signal must remain stable after an active reference signal change. In nets, a waveform must arrive a certain amount of time, t_setup, before the active clock edge, and be held a certain amount of time, t_hold, after the active clock
edge, in order for the input signal to be properly sampled. Hold time fixing is most of timing fixed process when implement design.
 

Re: Hold Time

To remove hold time you have to decrease the frequency of the clock (i.e. increasing the time period)..
 

Hold Time

hi

i have some confusion regarding hold time violation... i have asked to several person for that one. whether we can remove hold time violation by increasing/decreasing frequency. all d person told me different answers. some told me we can... but some told me we cant... can any body provide me any document related to this topic.. i have studied synopsys online document ...but still i have doubt..

Thanks N Regards
Deepak Agarwal
 

Re: Hold Time

deh_fuhrer said:
To remove hold time you have to decrease the frequency of the clock (i.e. increasing the time period)..
Click to expand...

Disagree the above statement.

To remove hold time violations, we add buffers in the data path.
 

Re: Hold Time

Decreasing the clock frequency will help with setup violations, but to fix hold violations you can either decrease your clock skew or delay your D-path as stated above.
 

Re: Hold Time

because hold time is the time for which you data need to be there after clock edge. so that depend on you data path delay. If you increase or decrease the freq, your delay will not be change. so the time for wich data will be there will not be change. you can remove hold violations using delaying your data path by means of inserting buffer or inv
 
Re: Hold Time

inserting buffers may violate setup-time...

Added after 6 minutes:

inserting buffers is a solution to remove hold-time violation...
but I am confused about decreasing frequency,as I have heard from someone that if delaying datapath doesnot work than you can only do one thing is to decrease frequency....
 

Hold Time

Does decreasing frequency helps to fix hold-time?
Certainly not. We all know that
Thold <= Tdata-min + Tc-q + (-) Tskew

Here Frequency is determined by Critical path delay (i.e., Tdata-max). So it happens that hold is skrewed by the fastest data which arrives in the next clock pulse. So it does n't have anything to do with clock period. So for fixing this hold problem we insert buffers in the min. delay data path btwn two registers.
 

Hold Time

As we know that
Th = tdm+tcq+tskew
so hold time is independent of clock frequency.
 

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